MC10EP445, MC100EP445

http://onsemi.com

8

Symbol

Characteristic

−40

°C

25

°C

85

°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Maximum Input CLK Frequency

CKSEL = LOW

CKSEL = HIGH

2.0

2.8

2.5

3.3

2.0

2.8

2.5

3.3

1.7

2.8

2.2

3.3

GHz

Propagation Delay to

CLK to Q

Output Differential

CLK TO PCLK

1280

1000

1475

1240

1710

1490

1335

1050

1557

1310

1795

1580

1450

1140

1663

1420

1950

1710

ps

ts

Setup Time

SINA, B+ TO CLK+ (Figure 5)

CKEN+ TO CLK− (Figure 6)

−400

100

−459

50

−420

100

−479

50

−440

100

−492

50

ps

Hold Time

CLK+ TO SINA, B− (Figure 5)

CLK− TO CKEN (Figure 6)

533

45

474

−35

550

45

490

−35

560

45

508

−35

ps

Reset Recovery (Figure 4)

350

180

350

180

350

180

ps

Minimum Pulse Width

RESET

400

400

400

ps

RMS Random Clock Jitter

@ 2.0 GHz CLK_SEL LOW

@ 2.5 GHz CLK_SELF HIGH

@ 3.0 GHz CLK_SEL HIGH

1.5

1.0

1.5

1.5

1.0

2.0

1.5

1.5

2.5

ps

Input Voltage Swing (Differential Configuration)

(Note 25)

150

800

1200

150

800

1200

150

800

1200

mV

Output Rise/Fall Times

Q/Q

(20% − 80%)

PCLK/PCLK

100

100

180

180

400

250

100

100

200

200

400

300

125

125

230

230

425

325

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

24. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50