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MC100EP05DR2G 数据表(PDF) 1 Page - ON Semiconductor |
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MC100EP05DR2G 数据表(HTML) 1 Page - ON Semiconductor |
1 / 11 page © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 10 1 Publication Order Number: MC10EP05/D MC10EP05, MC100EP05 3.3V / 5V ECL 2‐Input Differential AND/NAND Description The MC10/100EP05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 220 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: ♦ VCC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −3.0 V to −5.5 V • Open Input Default State • Safety Clamp on Inputs • Q Output Will Default LOW with Inputs Open or at VEE • These Devices are Pb-Free, Halogen Free and are RoHS Compliant A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package H = MC10 K = MC100 5I = MC10 2X = MC100 D = Date Code MARKING DIAGRAMS* ALYWG G HP05 ALYWG G KP05 1 8 1 8 www.onsemi.com HEP05 ALYWG G 1 8 KEP05 ALYWG G 1 8 14 14 (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information on page 8 of this data sheet. ORDERING INFORMATION SOIC−8NB D SUFFIX CASE 751−07 TSSOP−8 DT SUFFIX CASE 948R−02 1 8 1 8 DFN−8 MN SUFFIX CASE 506AA |
类似零件编号 - MC100EP05DR2G |
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类似说明 - MC100EP05DR2G |
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