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ADF4206BRU 数据表(PDF) 5 Page - Analog Devices

部件名 ADF4206BRU
功能描述  Dual RF PLL Frequency Synthesizers
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADF4206BRU 数据表(HTML) 5 Page - Analog Devices

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REV. 0
ADF4206/ADF4207/ADF4208
–5–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin
ADF4206/
No.
ADF4207
ADF4208
Function
1VDD1VDD1
Positive Power Supply for the RF1 Section. A 0.1
µF capacitor should be connected between
this pin and the RF1 ground pin, DGNDRF1. VDD1 should have a value of between 2.7 V and
5.5 V. VDD1 must have the same potential as VDD2.
2VP1VP1
Power Supply for the RF1 Charge Pump. This should be greater than or equal to VDD.
3CPRF1
CPRF1
Output from the RF1 Charge Pump. This is normally connected to a loop filter which, in
turn, drives the input to an external VCO.
4
DGNDRF1
DGNDRF1
Ground Pin for the RF1 Digital Circuitry.
5
RF1IN
RF1INA
Input to the RF1 Prescaler. This low-level input signal is normally taken from the RF1 VCO.
6
OSCIN
RFINB
Complementary Input to the RF1 Prescaler of the ADF4208. This point should be decoupled to
the ground plane with a small bypass capacitor.
7OSCOUT
AGNDRF1
Ground Pin for the RF1 Analog Circuitry.
8
MUXOUT
OSCIN
Oscillator Input. It has a VDD/2 threshold and can be driven from an external CMOS or TTL
logic gate.
9
CLK
OSCOUT
Oscillator Output.
10
DATA
MUXOUT
This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled
Reference Frequency to be accessed externally. See Table V.
11
LE
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 22-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
12
RF2IN
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
13
DGNDRF2
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected using the control bits.
14
CPRF2
AGNDRF2
Ground Pin for the RF2 Analog Circuitry.
15
VP2
RF2INB
Complementary Input to the RF2 Prescaler. This point should be decoupled to the ground
plane with a small bypass capacitor.
16
VDD2
RF2INA
Input to the RF2 Prescaler. This low-level input signal is normally ac-coupled to the
external VCO.
17
DGNDRF2
Ground Pin for the RF2, Digital, Interface, and Control Circuitry.
18
CPRF2
Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives
the input to an external VCO.
19
VP2
Power Supply for the RF2 Charge Pump. This should be greater than or equal to VDD.
20
VDD2
Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1
µF capacitor
should be connected between this pin and the RF2 ground Pin, DGNDRF2. VDD2 should
have a value between 2.7 V and 5.5 V. VDD2 must have the same potential as VDD1.
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD1
VP1
CPRF1
DGNDRF1
RF1IN
OSCIN
OSCOUT
MUXOUT
VDD2
VP2
CPRF2
DGNDRF2
RF2IN
LE
DATA
CLK
ADF4206/
ADF4207
TSSOP
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
ADF4208
VDD1
VP1
CPRF1
DGNDRF1
RF1IN A
OSCIN
OSCOUT
MUXOUT
VDD2
VP2
CPRF2
AGNDRF2
LE
DATA
CLK
RF1IN B
AGNDRF1
RF2IN B
RF2IN A
DGNDRF2


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