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TSC2301 数据表(PDF) 8 Page - Texas Instruments |
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TSC2301 数据表(HTML) 8 Page - Texas Instruments |
8 / 94 page www.ti.com TIMING DIAGRAM t td ta t sck tLead tLag twsck twsck tr tf tv tho tdis thi tsu MSB OUT BIT . . . 1 LSB OUT MSB IN BIT . . . 1 LSB IN SS SCLK MISO MOSI TIMING CHARACTERISTICS (1) (2) TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 PIN DESCRIPTION (continued) VFBGA TQFP I/O NAME DESCRIPTION BALL PIN D10 61 I Y+ Y+ position input C11 62 I HPVDD Analog supply for headphone amplifier and touch screen circuitry B11 63 I AUX1 SAR auxiliary analog input 1 B10 64 I AUX2 SAR auxiliary analog input 2 All specifications typical at -40°C to +85°C, +V DD = +2.7 V, POL = 1 Parameter Symbol Min Max Units SCLK period tsck 30 ns Enable lead time tLead 15 ns Enable lag time tLag 15 ns Sequential transfer delay ttd 30 ns Data setup time tsu 10 ns Data hold time (inputs) thi 10 ns Data hold time (outputs) tho 0 ns Slave access time ta 15 ns Slave DOUT disable time tdis 15 ns Data valid tv 10 ns Rise time tr 30 ns Fall time tf 30 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram, above. 8 |
类似零件编号 - TSC2301_15 |
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类似说明 - TSC2301_15 |
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