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CS98100-CM 数据表(PDF) 8 Page - Cirrus Logic |
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CS98100-CM 数据表(HTML) 8 Page - Cirrus Logic |
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8 / 60 page  CS98100 8 1.2.2 SDRAM Interface The CS98100 interfaces with either SDRAM or SGRAM, for high data bandwidth transfer. Figure 5 and Table 2 show the interface pin timing. Figure 2 shows the refresh cycle performed by the CS98100. Figure 3 shows a burst read (length = 8) transaction, while Figure 4 shows a burst write (length=8) trans- action. In both Figure 3 and Figure 4, CAS latency is programmed to 3. Symbol Description Min Typ Max Unit tmco Output Delay from DR_CKO active edge 9 ns tmper DR_CKO Period 11 12.2 ns tmdow DR_D[31:0] delay from DR_CKO 9.1 ns tmhw DR_D[31:0] valid time after DR_CKO 1.5 ns tmsur1 1.Delay is programmable by selecting the DRAM_Input_Speed bit of the Command Register(0x000) DR_D[31:0] setup to DR_CKO 3.9 ns tmsurd1 DR_D[31:0] setup to DR_CKO with delay 4.3 ns tmhr1 DR_D[31:0] hold time after DR_CKO 1.85 ns tmhrd1 DR_D[31:0] hold time after DR_CKO with delay 1.3 ns Table 2. SDRAM Interface Characteristics DR_CKO DR_A[11:0] DR_BS_N DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM_[3:0] DR_AP Figure 2. SDRAM Refresh Transaction |
类似零件编号 - CS98100-CM |
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类似说明 - CS98100-CM |
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