ADE7758ARWZRL datasheet(11/68 Pages) AD

部件名	ADE7758ARWZRL

功能描述	Poly Phase Multifunction Energy Metering IC with Per Phase Information

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制造商	AD [Analog Devices]

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ADE7758

Rev. A | Page 11 of 68

Pin No.

Mnemonic

Description

17

VARCF

Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information

depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and

calibration purposes. The full-scale output frequency can be scaled by writing to the VARCFNUM and

VARCFDEN registers (see the Reactive Power Frequency Output section).

18

IRQ

Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include: active

energy register at half level, apparent energy register at half level, and waveform sampling up to 26 kSPS (see

the ADE7758 Interrupts section).

19

CLKIN

Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.

Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock

source for the ADE7758. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of a

few tens of picofarad should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data

sheet for the load capacitance requirements

20

CLKOUT

A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the

ADE7758. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a

crystal is being used.

21

CS

Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7758 to share the serial

bus with several other devices (see the ADE7758 Serial Interface section).

22

DIN

Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK (see the ADE7758

Serial Interface section).

23

SCLK

Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock

(see the ADE7758 Serial Interface section). The SCLK has a Schmidt-trigger input for use with a clock source

which has a slow edge transition time, for example, opto-isolator outputs.

24

DOUT

Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output

is normally in a high impedance state, unless it is driving data onto the serial data bus (see the ADE7758 Serial

Interface section).

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