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74LVC273A 数据表(PDF) 5 Page - Diodes Incorporated

部件名 74LVC273A
功能描述  OCTAL D-TYPE FLIP-FLOP WITH CLEAR
Download  10 Pages
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制造商  DIODES [Diodes Incorporated]
网页  http://www.diodes.com
标志 DIODES - Diodes Incorporated

74LVC273A 数据表(HTML) 5 Page - Diodes Incorporated

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74LVC273A
Document number: DS35892 Rev. 1 - 2
5 of 10
www.diodes.com
June 2014
© Diodes Incorporated
74LVC273A
Switching Characteristics
Symbol
Parameter
Test Conditions
VCC
TA = +25°C
-40°C to +85°C
+85°C to +125°C
Unit
Min
Typ
Max
Min
Max
Min
Max
fMAX
Maximum
Frequency
Figure 1
1.8V ± 0.15V
35
40
35
30
Mhz
2.5V ± 0.3V
75
60
50
45
2.7V
150
175
150
100
3.3V ± 0.3
150
230
150
125
tW
Pulse Width
CLK
High or Low
Figure 1
1.8V ± 0.15V
5.0
2.5
5.0
5.5
ns
2.5V ± 0.3V
4.0
2.0
4.0
4.5
2.7V
3.3
1.7
3.3
3.5
3.3V ± 0.3V
3.0
1.5
3.0
3.5
tW
Pulse Width
CLR Low
Figure 1
1.8V ± 0.15V
5.0
2.5
5.0
5.5
ns
2.5V ± 0.3V
4.0
2.0
4.0
4.5
2.7V
3.3
1.7
3.3
3.5
3.3V ± 0.3V
3.0
1.5
3.0
3.5
tSU
Set-up Time DN
to CLK
Figure 1
1.8V ± 0.15V
4.0
2.0
4.0
4.5
tSU
ns
2.5V ± 0.3V
3.0
1.5
3.0
3.5
2.7V
2.0
1.0
2.0
2.5
3.3V ± 0.3V
1.5
1.0
1.5
2.0
tH
Hold Time
DN to CLK
Figure 1
1.8V ± 0.15V
3.0
1.5
3.0
3.5
ns
2.5V ± 0.3V
2.0
1.0
2.0
2.5
2.7V
1.5
1.0
1.5
2.0
3.3V ± 0.3V
1.5
1.0
1.5
2.0
tREM
Removal Time
CLR to CLK
Figure 1
1.8V ± 0.15V
1
7.8
16.5
1
17
1
14.2
ns
2.5V ± 0.3V
1
4
9
1
9.5
1
8.2
2.7V
1
4.4
8.3
1
8.5
1
10.0
3.3V ± 0.3V
1.7
4.1
7.3
1.7
7.5
1.7
9.0
tPD
Propagation
Delay
CLK to QN
Figure 1
1.8V ± 0.15V
1
7.8
16.5
1
17
1
14.2
ns
2.5V ± 0.3V
1
4
9
1
9.5
1
8.2
2.7V
1
4.4
8.3
1
8.5
1
10.0
3.3V ± 0.3V
1.7
4.1
7.3
1.7
7.5
1.7
9.0
tPD
Propagation
Delay
CLR to QN
Figure 1
1.8V ± 0.15V
1
7.8
16.5
1
17
1
14.2
ns
2.5V ± 0.3V
1
4
9
1
9.5
1
8.2
2.7V
1
4.4
8.3
1
8.5
1
10.0
3.3V ± 0.3V
1.7
4.1
7.3
1.7
7.5
1.7
9.0
tsk(0)
Output Skew
Time
3.3V ± 0.3V
1.0
1.5
ns
Operating Characteristics
TA = +25°C
Symbol
Parameter
Test Conditions
VCC
TYP
Unit
Cpd
Power dissipation
capacitance per gate
F = 10 MHz
1.8V ± 0.15V
9.9
pF
2.5V ± 0.3V
10.2
3.3V ± 0.3V
10.6
Package Characteristics
Symbol
Parameter
Package
Test Conditions
Min
Typ
Max
Unit
θJA
Thermal Resistance
Junction-to-Ambient
TSSOP-20
(Note 9)
74
°C/W
θJC
Thermal Resistance
Junction-to-Case
TSSOP-20
(Note 9)
15
°C/W
θJA
Thermal Resistance
Junction-to-Ambient
V-QFN4525-20
(Note 9)
67
°C/W
θJC
Thermal Resistance
Junction-to-Case
V-QFN4525-20
(Note 9)
20
°C/W
Note:
9. Test conditions for TSSOP-20 and V-QFN4525-20: Devices mounted on 4 layer FR-4 substrate PC board, 2oz copper, with minimum recommended
pad layout per JESD 51-7.


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