74ALVC374PW datasheet(2/20 Pages) PHILIPS

部件名	74ALVC374PW

功能描述	Octal D-type flip-flop positive edge-trigger

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制造商	PHILIPS [NXP Semiconductors]

网页	http://www.nxp.com

标志

2 / 20 page

2002 Feb 26

2

Philips Semiconductors

Product speciﬁcation

Octal D-type ﬂip-ﬂop; positive edge-trigger;

3-state

74ALVC374

FEATURES

• Wide supply voltage range from 1.65 to 3.6 V

• Complies with JEDEC standard:

JESD8-7 (1.65 to 1.95 V)

JESD8-5 (2.3 to 2.7 V)

JESD8B/JESD36 (2.7 to 3.6 V).

• 3.6 V tolerant inputs/outputs

• CMOS LOW power consumption

• Direct interface with TTL levels (2.7 to 3.6 V)

• Power-down mode

• Latch-up performance exceeds ≤250 mA

• ESD protection:

2000 V Human Body Model (JESD22-A 114-A)

200 V Machine Model (JESD22-A 115-A).

DESCRIPTION

The 74ALVC374 is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

The 74ALVC374 is an octal D-type flip-flop featuring

separate D-type inputs for each flip-flop and 3-state

outputs for bus oriented applications. A clock (CP) input

and an output enable (OE) input are common to all

flip-flops.

The eight flip-flops will store the state of their individual

D-inputs that meet the set-up and hold times requirements

on the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the eight flip-flops is

available at the outputs. When OE is HIGH, the outputs go

to the high-impedance OFF-state. Operation of the

OE input does not affect the state of the flip-flops.

The ‘374’ is functionally identical to the ‘574’, but the ‘574’

has a different pin arrangement.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi +(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

propagation delay CP to Qn

VCC = 1.8 V; CL = 30 pF; RL =1kΩ

3.1

ns

VCC = 2.5 V; CL = 30 pF; RL = 500 Ω

2.3

ns

VCC = 2.7 V; CL = 50 pF; RL = 500 Ω

2.5

ns

VCC = 3.3 V; CL = 50 pF; RL = 500 Ω

2.5

ns

CI

input capacitance

3.5

pF

CPD

power dissipation capacitance per buffer

VCC = 3.3 V; notes 1 and 2

outputs enable

21

pF

outputs disabled

13

pF

类似零件编号 - 74ALVC374PW

制造商	部件名	数据表	功能描述
NXP Semiconductors	74ALVC374PW	98Kb / 17P	Octal D-type flip-flop; positive-edge trigger; 3-state Rev. 02-17 October 2007
Nexperia B.V. All right...	74ALVC374PW	259Kb / 15P	Octal D-type flip-flop; positive-edge trigger; 3-state Rev. 3 - 30 April 2021

More results

类似说明 - 74ALVC374PW

制造商	部件名	数据表	功能描述
NXP Semiconductors	74LV574	121Kb / 12P	Octal D-type flip-flop; positive edge-trigger 3-State 1998 Jun 10
	74ALVC374	98Kb / 17P	Octal D-type flip-flop; positive-edge trigger; 3-state Rev. 02-17 October 2007
	74HC273-Q100	147Kb / 19P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 1-19 June 2013
Nexperia B.V. All right...	74LVC273-Q100	715Kb / 16P	Octal D-type flip-flop with reset; positive-edge trigger
	74HCT374	259Kb / 15P	Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 5 - 7 September 2021
	74HC574	289Kb / 17P	Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 9 - 20 October 2022
Unisonic Technologies	U74HCT574	177Kb / 5P	OCTAL D-TYPE EDGE-TRIGGER FLIP-FLOP
NXP Semiconductors	74ALVC574	99Kb / 17P	Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02-8 November 2007
	74AHC273	111Kb / 18P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 03-13 May 2008
	74LV273	117Kb / 12P	Octal D-type flip-flop with reset; positive-edge trigger 1998 May 29