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MC33HB2001FK 数据表(PDF) 5 Page - NXP Semiconductors |
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MC33HB2001FK 数据表(HTML) 5 Page - NXP Semiconductors |
5 / 48 page NXP Semiconductors MC33HB2001 10 A H-Bridge, SPI programmable brushed DC motor driver MC33HB2001 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved Data sheet: Advance information Rev. 6.0 — 3 May 2016 5 / 48 Symbol 32-pin SOICW 32-pin PQFN Pin function Definition ENBL 2 7 D_In When ENBL is logic HIGH, the H-Bridge is operational. When ENBL is logic LOW, the H-Bridge outputs are tri- stated and placed in Sleep mode. DIS 3 8 D_In When DIS is logic HIGH, both OUT1 and OUT2 are tri- stated IN2 4 9 D_In Logic input control of OUT2 IN1 5 10 D_In Logic input control of OUT1 CFB 6 11 A_Out The load current feedback output provides ground referenced 0.25 % of the high-side output current. FS_B 7 18 D_Out Open drain active LOW status flag output VPWR 8, 9, 24, 25 12, 13, 29, 30 Supply These pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the PCB. OUT1 10, 11 14, 15 A_Out Source of HS1 and drain of LS1 — 12, 13, 14, 20, 21 16, 17, 19, 25, 26 NC No connection to die or substrate PGND 15, 16, 17, 18 20, 21, 22, 23 GND Power ground for OUT1 and OUT2[1] OUT2 22, 23 27, 28 A_Out Source of HS2 and drain of LS2 CCP 26 31 A_Out External reservoir capacitor connection for the internal charge pump; connected to VPWR CS_B 27 32 D_In SPI control chip select bar input pin VDDQ 28 1 Supply Logic level bias MISO 29 2 D_Out Provides digital data from HB2001 to the MCU SCLK 30 3 D_In SPI control clock input pin MOSI 31 4 D_In SPI control data input pin from MCU DGND 32 5 GND Ground for logic[1] EP EP EP GND Thermal exposed pad – connected to substrate[1] [1] All PGND, AGND, DGND and EP pins must be connected together with very low-impedance on the PCB. 7.3 Functional pin description 7.3.1 Logic bias input (VDDQ) VDDQ supplies a level shifted bias voltage for the logic level outputs designed to be read by the microprocessor/microcontroller. This pin applies the logic supply voltage to MISO making the output logic levels compliant to logic systems from 3.3 V to 5.0 V. See Section 10.3 "VDDQ digital output supply voltage" for more details. 7.3.2 Supply voltage (VPWR) VPWR is the power supply input for the H-Bridge. The input voltage range with full performance is from 8.0 V to 28 V. In either case, the maximum allowable transient |
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