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ES1988 数据表(PDF) 4 Page - List of Unclassifed Manufacturers |
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ES1988 数据表(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 6 page 4 SAM0368-030601 ESS Technology, Inc. ES1988 PRODUCT BRIEF GD[3] 45 I/O Game port data input/output. ECLK O Clock output to EEPROM clock input. ECLK goes active after power-on reset and goes inactive automatically after EEPROM cycle is complete. VOLDN# I Hardware volume control (volume down). Used in combination with pin 44 (VOLUP#). Hardware volume control is enabled by setting PCI 52 [7] = 1. Pins 44:45 are selected for hardware volume control by setting PCI 52h [5] = 1. Pins 53:54 may also be used for hardware volume control. GD[4] 46 I Game port data input. GD[5:7] 47:49 I Game port data input. GPIO[13:15] I/O General-purpose input/output. I2SCLK 50 I I2S serial clock input. I2S input is enabled by setting Allegro_Base+37h [15] = 1. SIRQ# I/O Serial interrupt request. Optional PC/PCI system implementation. Serial IRQ is enabled by setting PCI 40h [14] = 1. GPIO4 I/O General-purpose input/output. I2SLR 51 I I2S frame sync input. I2S input is enabled by setting Allegro_Base+37h [15] = 1. GTO# O Grant to PCI master. GTO# is enabled by setting PCIx2 arbiter bits PCI 58h [0] = 1 and PCI 58h [11] = 1. Select GT0#/GSO from pin 51 by enabling PCI 58h [10] = 0. Pin 63 may also be used as GT0#/GSO. GSO O Grant select 0 output to control external quick switch to grant PCI master phase. GSO is enabled by setting PCIx2 arbiter bit PCI 58h [0] = 1 and PCI 58h [11] = 0. Select GS0/GT0# from pin 51 by enabling PCI 58h [10] = 0. Pin 63 may also be used as GT0#/GSO. GPIO5 I/O General-purpose input/output. I2SDATA 52 I I2S data input. I2S input is enabled by setting Allegro_Base+37h [15] = 1. R0# I PCI bus request 0 input from external PCI master device. RO# is enabled by setting the PCIx2 arbiter bit PCI 58h [0] = 1. Select R0# from pin 52 by enabling PCI 58h [10] = 0. Either pin 2 or pin 52 may be used for R0#. GPIO6 I/O General-purpose input/output. MC_97DI 53 I Modem codec data input. Enabled by setting Allegro_Base+38h [3] = 1. PCREQ# O PC/PCI request output. Enable PCREQ# by setting PCI 50h [10:8] = 010. Pin 53 is used as PCREQ# when configured as an audio-only device. PCREQ# can only be used from pin 2 when configured as a multifunction device (see pin 60 note). VOLUP# I Hardware volume control (volume up). Used in combination with pin 54 (VOLDN#). Hardware volume control is enabled by setting PCI 52 [7] = 1. Pins 53:54 are selected for hardware volume control by setting PCI 52h [5] = 0. Pins 44:45 may also be used for hardware volume control. GPIO7 I/O General-purpose input/output. PME# 54 O PME# output to wake the system. PME is enabled by setting the PME_EN bit (PCI C5h [0] = 1). SPDIFO O S/PDIF output. Enable SPDIFO by setting PCI 53h [0] = 1. Select SPDIFO from pin 54 by setting PCI 58h [1] = 0. Either pin 2 or pin 54 may be used for SPDIFO. PCGNT# I PC/PCI grant input. Enable PC/PCI by setting PCI 50h [10:8] = 010. Select PCGNT# from pin 54 by setting Allegro_Base+58h [6] = 1. Either pin 54 or pin 63 may be used for PCGNT#. VOLDN# I Hardware volume control (volume down). Used in combination with pin 53 (VOLUP#). Hardware volume control is enabled by setting PCI 52 [7] = 1. Pins 53:54 are selected for hardware volume control by setting PCI 52h [5] = 0. Pins 44:45 may also be used for hardware volume control. VAUX 55 I 3.3V VAUX voltage supply input. If VAUX is not supported, then VAUX (pin 55) should be con- nected to VCC and VAUXD (pin 62) should be pulled down. Table 1 ES1988 Pin Descriptions (Continued) Names Pin Numbers I/O Descriptions |
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