Si5380-D-EVB datasheet(2/53 Pages) SILABS

部件名	Si5380-D-EVB

功能描述	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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制造商	SILABS [Silicon Laboratories]

网页	http://www.silabs.com

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2 / 53 page

1. Feature List

The Si5380-D features are listed below:

• Digital frequency synthesis eliminates external VCXO and an-

alog loop filter components

• Supports JESD204B clocking: DCLK and SYSREF

• Ultra-low jitter:

• 65 fs typ (12 kHz to 20 MHz)

• Input frequency range:

• Differential: 11.52 MHz to 737.28 MHz

• LVCMOS: 11.52 MHz to 245.76 MHz

• Output frequency range:

• Differential: up to 1.47456 GHz

• LVCMOS: up to 245.76 MHz

• Phase noise floor: –159 dBc/Hz

• Spur performance: –103 dBc max (relative to a 122.88 MHz

carrier)

• Configurable outputs:

• Signal swing: 200 to 3200 mVpp

• Compatible with LVDS, LVPECL

• LVCMOS 3.3, 2.5, or 1.8 V

• Output-output skew using same N-divider: 65 ps (Max)

• Adjustable output-output delay: 68 ps/step, ±128 steps

• Optional Zero Delay mode

• Independent output clock supply pins: 3.3, 2.5, or 1.8 V

• Core voltage:

• VDD = 1.8 V ±5%

• VDDA = 3.3 V ±5%

• Automatic free-run, lock, and holdover modes

• Programmable jitter attenuation bandwidth: 0.1 Hz to 100 Hz

• Hitless input clock switching

• Status monitoring (LOS, OOF, LOL)

• Serial interface: I2C or SPI In-circuit programmable with non-

volatile OTP memory

• ClockBuilderTM Pro software tool simplifies device configura-

tion

• Si5380: 4 input, 12 output, 64-QFN 9×9 mm

• Temperature range: –40 to +85 °C

• Pb-free, RoHS-6 compliant

Si5380 Rev D Data Sheet

Feature List

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Rev. 1.0 | 1

类似零件编号 - Si5380-D-EVB

制造商	部件名	数据表	功能描述
Silicon Laboratories	Si5380-D-EVB	1Mb / 53P	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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类似说明 - Si5380-D-EVB

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