SN54ABTH32316, SN74ABTH32316

16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS

SCBS179E – JUNE 1992 – REVISED MAY 1997

2

POST OFFICE BOX 655303

SN54ABTH32316 ...HT PACKAGE

(TOP VIEW)

23 24

C8

C7

C6

GND

C5

C4

C3

C2

C1

NC

GND

B16

B15

B14

B13

B12

GND

B11

B10

B9

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

A2

A3

A4

GND

A5

A6

A7

A8

A9

NC

GND

A10

A11

A12

A13

A14

GND

A15

A16

NC

26 27 28 29

83 82 81 80 79

84

78

76 75 74

77

30 31 32 33 34

73 72

22

71 70 69 68

35 36 37 38 39 40 41 42

67 66 65 64

NC – No internal connection

description

The ’ABTH32316 consist of three 16-bit registered input/output (I/O) ports. These registers combine D-type

latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be

exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations

of real-time and stored data can be exchanged among the three ports.

Data flow in each direction is controlled by the output-enable (OEA, OEB, and OEC), select-control (SELA,

SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data

register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held

at a high or low logic level. If LEA and clock-enable A (CLKENA) are low, data is stored on the low-to-high

transition of CLKA. Output data selection is accomplished by the select-control pins. All three ports have

active-low output enables, so when the output-enable input is low, the outputs are active; when the

output-enable input is high, the outputs are in the high-impedance state.

the minimum value of the resistor is determined by the current-sinking capability of the driver.