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TPD3S014-Q1 数据表(PDF) 11 Page - Texas Instruments |
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TPD3S014-Q1 数据表(HTML) 11 Page - Texas Instruments |
11 / 28 page OUT IN EN Control Logic + Charge Pump Current Limit UVLO Thermal Sense Back Gate Control Copyright © 2016, Texas Instruments Incorporated 11 TPD3S014-Q1 www.ti.com SLVSDG5B – MARCH 2016 – REVISED APRIL 2016 Product Folder Links: TPD3S014-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The TPD3S014-Q1 is a highly integrated device that features a current limited load switch and a two-channel TVS based ESD protection diode array for USB interfaces. The TPD3S014-Q1 provides 0.5 A of continuous load current in 5 V circuits. This part uses N-channel MOSFETs for low resistance, maintaining voltage regulation to the load. It is designed for applications where short circuits or heavy capacitive loads will be encountered. Device features include enable, reverse blocking when disabled, output discharge pull-down, over-current protection, and over-temperature protection. Finally, with two channels of TVS ESD protection diodes integrated, the TPD3S014-Q1 provides system level ESD protection to all the pins of the USB port. 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Undervoltage Lockout (UVLO) The UVLO circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted on and off cycling becuase of input voltage drop from large current surges. 8.3.2 Enable The logic enable input (EN) controls the power switch, bias for the charge pump, driver, and other circuits. The supply current is reduced to less than 1 µA when the TPD3S014-Q1 is disabled. The enable input is compatible with both TTL and CMOS logic levels. The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times are internally controlled. The rise time is controlled by both the TPD3S014-Q1 and the external loading (especially capacitance). The TPD3S014-Q1 fall time is controlled by the loading (R and C), and the output discharge (RPD). An output load consisting of only a resistor experiences a fall time set by the TPD3S014-Q1. An output load with parallel R and C elements experiences a fall time determined by the (R × C) time constant if it is longer than the TPD3S014-Q1 tF. See Figure 21 and Figure 22 showing tR, tF, tON, and tOFF. The enable must not be left open; it may be tied to VIN. |
类似零件编号 - TPD3S014-Q1 |
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类似说明 - TPD3S014-Q1 |
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