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TP3054WM-X63 数据表(PDF) 2 Page - Texas Instruments |
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TP3054WM-X63 数据表(HTML) 2 Page - Texas Instruments |
2 / 22 page TP3054-X, TP3057-X SNOSBY2C – MARCH 2005 – REVISED APRIL 2013 www.ti.com Block Diagram Figure 3. PIN DESCRIPTIONS Symbol Function VBB Negative power supply pin. VBB = −5V ±5%. GNDA Analog ground. All signals are referenced to this pin. VFRO Analog output of the receive power amplifier. VCC Positive power supply pin. VCC = +5V ±5%. Receive frame sync pulse which enables BCLKR to shift PCM data into DR. FSR is an 8 kHz FSR pulse train. See Figure 4 and Figure 5 for timing details. DR Receive data input. PCM data is shifted into DR following the FSR leading edge. The bit clock which shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or BCLKR/CLKSEL 2.048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive directions (see Table 1). Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKX, but should be synchronous with MCLKX for best performance. When MCLKR is MCLKR/PDN connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous MCLKX with MCLKR. Best performance is realized from synchronous operation. Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on DX. FSX is FSX an 8 kHz pulse train, see Figure 4 and Figure 5 for timing details. The bit clock which shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must BCLKX be synchronous with MCLKX. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: TP3054-X TP3057-X |
类似零件编号 - TP3054WM-X63 |
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类似说明 - TP3054WM-X63 |
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