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TL16C2552IFNR 数据表(PDF) 11 Page - Texas Instruments |
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TL16C2552IFNR 数据表(HTML) 11 Page - Texas Instruments |
11 / 34 page www.ti.com ELECTRICAL CHARACTERISTICS TIMING REQUIREMENTS BAUD GENERATOR SWITCHING CHARACTERISTICS TL16C2552 SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 5 V Nominal PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VOH High-level output voltage(2) IOH = -4 mA 4 V VOL Low-level output voltage(2) IOL = 4 mA 0.4 V II Input current VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V, All other 10 µA terminals floating IOZ High-impedance-state output VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V, Chip selected in ±20 µA current write mode or chip deselected ICC Supply current VCC = 5.5 V, TA = 0°C, RXA, RXB, DSRA, DSRB, 7.5 mA CDA, CDB, CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, XTAL1 at 24 MHz, No load on outputs Ci(CLK) Clock input impedance 15 20 pF CO(CLK) Clock output impedance 20 30 pF VCC = 0, VSS = 0, f = 1 MHz, TA = 25°C, All other terminals grounded CI Input impedance 6 10 pF CO Output impedance 10 20 pF (1) All typical values are at VCC = 5 V and TA = 25°C. (2) These parameters apply for all outputs except XTAL2. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LIMITS ALT. TEST PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX tw8 Pulse duration, RESET tRESET 1 1 1 1 µs tw1 Pulse duration, clock high tXH 6 40 25 20 18 ns tw2 Pulse duration, clock low tXL tcR Cycle time, read (tw7 + td8 + th7) RC 8 115 80 62 57 ns tcW Cycle time, write (tw6 + td5 + th4) WC 7 115 80 62 57 ns tw6 Pulse duration, IOW or CS tIOW 7 80 55 45 40 ns tw7 Pulse duration, IOR or CS tIOR 8 80 55 45 40 ns tSU3 Setup time, data valid before IOW ↑ or CS↑ tDS 7 25 20 15 15 ns th4 Hold time, address valid after IOW ↑ or CS↑ tWA 7 20 15 10 10 ns th5 Hold time, data valid after IOW ↑ or CS↑ tDH 7 15 10 5 5 ns th7 Hold time, data valid after IOR ↑ or CS↑ tRA 8 20 15 10 10 ns td5 Delay time, address valid before IOW ↓ or CS↓ tAW 7 15 10 7 7 ns td8 Delay time, address valid to IOR ↓ or CS↓ tAR 8 15 10 7 7 ns td10 Delay time, IOR ↓ or CS↓ to data valid tRVD 8 CL = 30 pF 55 35 25 20 ns td11 Delay time, IOR ↑ or CS↑ to floating data tHZ 8 CL = 30 pF 40 30 20 20 ns td12 Write cycle to write cycle delay 7 100 75 60 50 ns td13 Read cycle to read cycle delay 8 100 75 60 50 ns over recommended ranges of supply voltage and operating free-air temperature, C L = 30 pF (for FN package only) LIMITS ALT. TEST PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX tw3 Pulse duration, BAUDOUT low tLW 6 CLK ÷ 2 80 50 42 35 ns tw4 Pulse duration, BAUDOUT high tHW 6 CLK ÷ 2 80 50 42 35 ns td1 Delay time, XIN ↑ to BAUDOUT↑ tBLD 6 55 40 30 25 ns td2 Delay time, XIN ↑↓ to BAUDOUT↓ tBHD 6 55 40 30 25 ns 11 Submit Documentation Feedback |
类似零件编号 - TL16C2552IFNR |
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类似说明 - TL16C2552IFNR |
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