MYSON-CENTURY

TECHNOLOGY

MTV412M

(Rev 0.9)

Revision 0.9

- 10 -

April 2002

PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is

253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high

output. If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing

00H to DAC register generates stable low output.

Reg name

addr

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

DA0

F20h(r/w)

Pulse width of PWM DAC 0

DA1

F21h(r/w)

Pulse width of PWM DAC 1

DA2

F22h(r/w)

Pulse width of PWM DAC 2

DA3

F23h(r/w)

Pulse width of PWM DAC 3

DA4

F24h(r/w)

Pulse width of PWM DAC 4

DA5

F25h(r/w)

Pulse width of PWM DAC 5

DA6

F26h(r/w)

Pulse width of PWM DAC 6

DA7

F27h(r/w)

Pulse width of PWM DAC 7

DA8

F28h(r/w)

Pulse width of PWM DAC 8

DA9

F29h(r/w)

Pulse width of PWM DAC 9

DA10

F2Ah(r/w)

Pulse width of PWM DAC 10

DA11

F2Bh(r/w)

Pulse width of PWM DAC 11

DA12

F2Ch(r/w)

Pulse width of PWM DAC 12

DA13

F2Dh(r/w)

Pulse width of PWM DAC 13

DA0-13 (r/w) :

The output pulse width control for DA0-13.

* All of PWM DAC converters are centered with value 80h after power on.

6. H/V SYNC Processing

The H/V SYNC processing block performs the functions of composite signal separation/insertion. SYNC

inputs presence check, frequency counting, polarity detection and control, as well as the protection of

VBLANK output while VSYNC speeds up in high DDC communication clock rate.

Based on the digital filter, the HSYNC present and frequency function block treat any pulse longer than the

specified time period as pulse, and the specified time period is controlled by (DF1,DF0) bits. The VSYNC

digital filter has no control bit. It works as (DF1,DF0) = (0, 0) of HSYNC.