SN54HCT125, SN74HCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS069E – NOVEMBER 1988 – REVISED AUGUST 2003

1

POST OFFICE BOX 655303

LSTTL Loads

Lines or Buffer Memory Address Registers

SN54HCT125 ...J OR W PACKAGE

SN74HCT125 ...D OR N PACKAGE

(TOP VIEW)

32 1 20 19

910 11 1213

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3OE

1Y

NC

2OE

NC

2A

SN54HCT125 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y

description/ordering information

These bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE) input is high.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

–40 C to 85 C

PDIP – N

Tube of 25

SN74HCT125N

SN74HCT125N

–40

°C to 85°C

SOIC – D

Tube of 50

SN74HCT125D

HCT125

–40

°C to 85°C

SOIC – D

Reel of 2500

SN74HCT125DR

HCT125

Reel of 250

SN74HCT125DT

–55 C to 125 C

CDIP – J

Tube of 25

SNJ54HCT125J

SNJ54HCT125J

–55

°C to 125°C

CFP – W

Tube of 150

SNJ54HCT125W

SNJ54HCT125W

LCCC – FK

Tube of 55

SNJ54HCT125FK

SNJ54HCT125FK

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Copyright

 2003, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.