74AVC16834DGVRE4 datasheet(1/17 Pages) TI1

部件名	74AVC16834DGVRE4

功能描述	18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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制造商	TI1 [Texas Instruments]

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0.8

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2.8

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2.4

2.8

3.2

TA = 25°C

Process = Nominal

IOL - Output Current - mA

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

TA = 25°C

Process = Nominal

IOH - Output Current - mA

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

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SN74AVC16834

18-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES183H – DECEMBER 1998 – REVISED JUNE 2005

•

Overvoltage-Tolerant Inputs/Outputs Allow

Mixed-Voltage-Mode Data Communications

•

Member of the Texas Instruments Widebus™

Family

•

Ioff Supports Partial-Power-Down Mode

Operation

•

DOC™ (Dynamic Output Control) Circuit

Dynamically Changes Output Impedance,

•

ESD Protection Exceeds JESD 22

Resulting in Noise Reduction Without Speed

– 2000-V Human-Body Model (A114-A)

Degradation

– 200-V Machine Model (A115-A)

•

Dynamic Drive Capability Is Equivalent to

•

Latch-Up Performance Exceeds 100 mA Per

Standard Outputs With IOH and IOL of ±24 mA

JESD 78, Class II

at 2.5-V VCC

A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output

impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows

typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At

the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a

high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family

Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry

Technology and Applications, literature number SCEA009.

Figure 1. Output Voltage vs Output Current

This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to

3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode

when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low

logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is

high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, DOC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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