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SN74ACT3632-20PQ 数据表(PDF) 10 Page - Texas Instruments |
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SN74ACT3632-20PQ 数据表(HTML) 10 Page - Texas Instruments |
10 / 30 page SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224D – JUNE 1992 – REVISED APRIL 1998 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 almost-empty flags (AEA, AEB) The AE flag of a FIFO is synchronized to the port clock that reads data from its array. The almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset programming). An AE flag is low when its FIFO contains X or fewer words and is high when its FIFO contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory. Two low-to-high transitions of the AE flag synchronizing clock are required after a FIFO write for its AE flag to reflect the new level of fill. Therefore, the AE flag of a FIFO containing (X + 1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An AE flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an AE flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 11 and 12). almost-full flags (AFA, AFB) The AF flag of a FIFO is synchronized to the port clock that writes data to its array. The almost-full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset programming). An AF flag is low when its FIFO contains (512 – Y) or more words and is high when its FIFO contains [512 – (Y + 1)] or fewer words. A data word is present in the FIFO output register has been read from memory. Two low-to-high transitions of the AF flag synchronizing clock are required after a FIFO read for its AF flag to reflect the new level of fill. Therefore, the AF flag of a FIFO containing [512 – (Y + 1)] or fewer words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [512 – (Y + 1)]. An AF flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [512 – (Y + 1)]. A low-to-high transition of an AF flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in memory to [512 – (Y + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 13 and 14). mailbox registers Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port-data-transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA and with MBA high. A low-to-high transition on CLKB writes B0 – B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port mailbox select input is low and from the mail register when the port-mailbox select input is high. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA and with MBA high. The data in a mail register remains intact after it is read and changes only when new data is written to the register. |
类似零件编号 - SN74ACT3632-20PQ |
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类似说明 - SN74ACT3632-20PQ |
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