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SN74AHCT367PWR 数据表(PDF) 8 Page - Texas Instruments

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部件名 SN74AHCT367PWR
功能描述  Hex Buffer and Line Driver with 3-State Output
Download  22 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

SN74AHCT367PWR 数据表(HTML) 8 Page - Texas Instruments

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1OE
To Three Other Channels
1A1
1Y1
2OE
To One Other Channel
2A1
2Y1
SN74AHCT367
SCLS418H – JUNE 1998 – REVISED DECEMBER 2014
www.ti.com
9 Detailed Description
9.1 Overview
The SN74AHCT367 device is designed specifically to improve both the performance and density of
3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device is
organized as a dual 4-line and 2-line buffer/driver with active-low output-enable (1OE and 2OE) inputs. When OE
is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are
in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
Figure 3. Logic Diagram (Positive Logic)
9.3 Feature Description
VCC is optimized at 5 V
Allows up voltage translation from 3.3 V to 5 V
Inputs Accept VIH levels of 2 V
Slow edge rates minimize output ringing
Inputs are TTL-Voltage compatible
9.4 Device Functional Modes
Table 1. Function Table
(Each Buffer/Driver)
INPUTS
OUTPUT
Y
OE
A
H
X
Z
L
H
H
L
L
L
8
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Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT367


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