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SN74AHCT367PWG4 数据表(PDF) 8 Page - Texas Instruments |
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SN74AHCT367PWG4 数据表(HTML) 8 Page - Texas Instruments |
8 / 22 page 1OE To Three Other Channels 1A1 1Y1 2OE To One Other Channel 2A1 2Y1 SN74AHCT367 SCLS418H – JUNE 1998 – REVISED DECEMBER 2014 www.ti.com 9 Detailed Description 9.1 Overview The SN74AHCT367 device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device is organized as a dual 4-line and 2-line buffer/driver with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagram Figure 3. Logic Diagram (Positive Logic) 9.3 Feature Description • VCC is optimized at 5 V • Allows up voltage translation from 3.3 V to 5 V – Inputs Accept VIH levels of 2 V • Slow edge rates minimize output ringing • Inputs are TTL-Voltage compatible 9.4 Device Functional Modes Table 1. Function Table (Each Buffer/Driver) INPUTS OUTPUT Y OE A H X Z L H H L L L 8 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT367 |
类似零件编号 - SN74AHCT367PWG4 |
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类似说明 - SN74AHCT367PWG4 |
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