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SN74AHCT86NSR 数据表(PDF) 10 Page - Texas Instruments

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部件名 SN74AHCT86NSR
功能描述  Quadruple 2-Input Exclusive-OR Gates
Download  30 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

SN74AHCT86NSR 数据表(HTML) 10 Page - Texas Instruments

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Vcc
Unused Input
Input
Output
Input
Unused Input
Output
SN54AHCT86, SN74AHCT86
SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014
www.ti.com
Typical Application (continued)
10.2.3 Application Curves
Figure 5. Up Translation
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1
μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1
μF and 1
μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 6 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs
section of the part when asserted. This will not disable the input section of the IOs so they cannot float when
disabled.
12.2 Layout Example
Figure 6. Layout Diagram
10
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Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHCT86 SN74AHCT86


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