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LM3503SQ-35 数据表(PDF) 3 Page - Texas Instruments |
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LM3503SQ-35 数据表(HTML) 3 Page - Texas Instruments |
3 / 28 page LM3503 www.ti.com SNVS329E – JULY 2005 – REVISED MAY 2013 Drain connection of the internal power NMOS FET switch (Figure 3: N1). Minimize the metal trace length and maximize the metal trace width connected to this pin to reduce EMI radiation and trace resistance. Pgnd (Bump D3): Power ground pin. Connect directly to the ground plane. Agnd (Bump C3):Analog ground pin. Connect the analog ground pin directly to the Pgnd pin. VIN (Bump B3): Input voltage connection pin. The CIN capacitor should be as close to the device as possible, between the VIN pin and ground plane. En2 (Bump A3): Enable pin for the internal NMOS FET switch (Figure 3: N2) during device operation. When VEn2 is ≥ 1.4V, the internal NMOS FET switch turns off and the SUB display is turned on. The En2 pin has an internal pull down circuit, thus the internal NMOS FET switch is normally in the on state of operation with the SUB display turned off. When VEn2 is ≤ 0.3V, the internal NMOS FET switch turns on and the SUB display is turned off. If both VEn1 and VEn2 are ≤ 0.3V the LM3503 will shutdown. If VOUT2 is not used, En2 must be floating or grounded and En1 used to enable the device. En1 (Bump A2): Enable pin for the internal PMOS FET switch (Figure 3: P1) during device operation. When VEn1 is ≤ 0.3V, the internal PMOS FET switch turns on and the MAIN display is turned off. When VEn1 is ≥ 1.4V, the internal PMOS FET switch turns off and the MAIN display is turned on. If both VEn1 and VEn2 are ≤ 0.3V the LM3503 will shutdown. The En1 pin has an internal pull down circuit, thus the internal PMOS FET switch is normally in the on state of operation with the MAIN display turned off. If VOUT2 is not used, En2 must be grounded and En1 use to enable the device. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN Pin −0.3V to +5.5V Sw Pin −0.3V to +48V Fb Pin −0.3V to +5.5V Cntrl Pin −0.3V to +5.5V VOUT1Pin −0.3V to +48V VOUT2 Pin −0.3V to VOUT1 En1 −0.3V to +5.5V En2 −0.3V to +5.5V Continuous Power Dissipation Internally Limited Maximum Junction Temperature (TJ-MAX) +150°C Storage Temperature Range −65°C to +150°C ESD Rating(3) Human Body Model 2 kV Machine Model 200V (1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical characteristic specifications do not apply when operating the device outside of its rated operating conditions. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. (3) The human body model is a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Operating Conditions (1) (2) Junction Temperature (TJ) Range −40°C to +125°C Ambient Temperature (TA) Range −40°C to +85°C Supply Voltage, VIN Pin 2.5V to 5.5V En1 and En2 Pins 0V to 5.5V Cntrl Pin 0V to 3.5V (1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical characteristic specifications do not apply when operating the device outside of its rated operating conditions. (2) All voltages are with respect to the potential at the GND pin. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM3503 |
类似零件编号 - LM3503SQ-35 |
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类似说明 - LM3503SQ-35 |
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