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LM3503SQ-35 数据表(PDF) 2 Page - Texas Instruments |
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LM3503SQ-35 数据表(HTML) 2 Page - Texas Instruments |
2 / 28 page A1 A2 A3 B1 B3 C1 C3 D1 D2 D3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LM3503 SNVS329E – JULY 2005 – REVISED MAY 2013 www.ti.com DESCRIPTION (CONTINUED) With no external compensation, cycle-by-cycle current limit, output over-voltage protection, input under-voltage protection, and dynamic white LED current control capability, the LM3503 offers superior performance over other step-up white LED drivers. Connection Diagram Figure 1. 10-Bump Thin DSBGA Package Figure 2. 16-Lead Thin WQFN Package (YPA0010) (Top View) (RGH0016A) (Top View) PIN DESCRIPTIONS Bump # Pin # Name Description A1 9 Cntrl White LED Current Control Connection B1 7 Fb Feedback Voltage Connection C1 6 VOUT2 Drain Connections of the NMOS and PMOS Field Effect Transistor (FET) Switches (Figure 3: N2 and P1). Connect 100nF at VOUT2 node if VOUT2 is not used D1 4 VOUT1 Over-Voltage Protection (OVP) and Source Connection of the PMOS FET Switch (Figure 3: P1) D2 2 and 3 Sw Drain Connection of the Power NMOS Switch (Figure 3: N1) D3 15 and 16 Pgnd Power Ground Connection C3 14 Agnd Analog Ground Connection B3 13 VIN Input Voltage Connection A3 12 En2 NMOS FET Switch Control Connection A2 10 En1 PMOS FET Switch Control Connection 1 NC No Connection 5 NC No Connection 8 NC No Connection 11 NC No Connection DAP DAP Die Attach Pad (DAP), to be soldered to the printed circuit board’s ground plane for enhanced thermal dissipation. Cntrl (Bump A1): White LED current control pin. Use this pin to control the feedback voltage with an external DC voltage. Fb (Bump B1):Output voltage feedback connection. VOUT2 (Bump C1):Drain connections of the internal PMOS and NMOS FET switches (Figure 3: P1 and N2). It is recommended to connect 100nF at VOUT2 if VOUT2 is not used for LM3503-35V & LM3503-44V versions. VOUT1(Bump D1): Source connection of the internal PMOS FET switch (Figure 3: P1) and OVP sensing node. The output capacitor must be connected as close to the device as possible, between the VOUT1 pin and ground plane. Also connect the Schottky diode as close as possible to the VOUT1 pin to minimize trace resistance and EMI radiation. Sw (Bump D2): 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM3503 |
类似零件编号 - LM3503SQ-35 |
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类似说明 - LM3503SQ-35 |
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