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SN74ALS653DWR 数据表(PDF) 4 Page - Texas Instruments |
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SN74ALS653DWR 数据表(HTML) 4 Page - Texas Instruments |
4 / 33 page SN54ALS652, SN54ALS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Function Tables SN54ALS653, SN54AS651, SN74ALS651A, SN74ALS653, SN74AS651 INPUTS DATA I/O† OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1– A8 B1– B8 OPERATION OR FUNCTION L H H or L H or L X X Input Input Isolation L H ↑↑ X X Input Input Store A and B data X H ↑ H or L X X Input Unspecified‡ Store A, hold B H H ↑↑ X‡ X Input Output Store A in both registers L X H or L ↑ X X Unspecified‡ Input Hold A, store B L L ↑↑ XX‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus and stored B data to A bus † The data output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs. ‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers. SN54ALS652, SN54AS652, SN74ALS652A, SN74ALS654, SN74AS652 INPUTS DATA I/O† OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1– A8 B1– B8 OPERATION OR FUNCTION L H H or L H or L X X Input Input Isolation L H ↑↑ X X Input Input Store A and B data X H ↑ H or L X X Input Unspecified‡ Store A, hold B H H ↑↑ X‡ X Input Output Store A in both registers L X H or L ↑ X X Unspecified‡ Input Hold A, store B L L ↑↑ XX‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus and stored B data to A bus † The data output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs. ‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers. |
类似零件编号 - SN74ALS653DWR |
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类似说明 - SN74ALS653DWR |
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