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SM320C31GFAS60 数据表(PDF) 8 Page - Texas Instruments |
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SM320C31GFAS60 数据表(HTML) 8 Page - Texas Instruments |
8 / 55 page SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL TYPE† DESCRIPTION CONDITIONS WHEN NAME QTY TYPE† DESCRIPTION WHEN SIGNAL IS Z TYPE‡ SUPPLY AND OSCILLATOR SIGNALS H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S VDD 20 I 5-V supply for ’C31 devices and 3.3-V supply for ’LC31 devices. All must be connected to a common supply plane.§ VSS 25 I Ground. All grounds must be connected to a common ground plane. X1 1 O Output from the internal-crystal oscillator. If a crystal is not used, X1 should be left unconnected. X2 / CLKIN 1 I Internal-oscillator input from a crystal or a clock RESERVED¶ EMU2 − EMU0 3 I Reserved for emulation. Use pullup resistors to VDD EMU3 1 O/Z Reserved for emulation S † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor value is 0.1 µF. ¶ Follow the connections specified for the reserved pins. Use 18-kΩ−22-kΩ pullup resistors for best results. All VDD supply pins must be connected to a common supply plane, and all ground pins must be connected to a common ground plane. Not Recommended for New Designs |
类似零件编号 - SM320C31GFAS60 |
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类似说明 - SM320C31GFAS60 |
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