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ADV7301A 数据表(PDF) 5 Page - Analog Devices

部件名 ADV7301A
功能描述  Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV??12-Bit DACs
Download  68 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7301A 数据表(HTML) 5 Page - Analog Devices

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REV. A
ADV7300A/ADV7301A
–5–
TIMING SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Test Conditions
MPU PORT
1
SCLOCK Frequency
0
400
kHz
SCLOCK High Pulsewidth, t1
0.6
µs
SCLOCK Low Pulsewidth, t2
1.3
µs
Hold Time (Start Condition), t3
0.6
µs
First Clock Generated after
This Period
Setup Time (Start Condition), t4
0.6
µsRelevant for Repeated Start
Condition
Data Setup Time, t5
100
ns
SDATA, SCLOCK Rise Time, t6
300
ns
SDATA, SCLOCK Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
0.6
µs
RESET Low Time
100
ns
ANALOG OUTPUTS
Analog Output Delay
2
8ns
Output Skew
1
ns
CLOCK CONTROL AND PIXEL PORT
3
fCLK
27
MHz
Progressive Scan Mode
fCLK
81
MHz
HDTV Mode/Async Mode
Clock High Time, t9
40
% 1 clkcycle
Clock Low Time, t10
40
% 1 clkcycle
Data Setup Time, t11
2.0
ns
Data Hold Time, t12
2.0
ns
Output Access Time, t13
14
ns
Output Hold Time, t14
4.0
ns
Pipeline Delay
61
clkcycles
SD [2 ]
62.5
clkcycles
SD [8 ]
66.5
clkcycles
SD Component Filter [8 ]
33
clkcycles
PS [1 ], HD [1 ], Async
Timing Mode
43.5
clkcycles
PS [4 ]
36
clkcycles
HD [2 ]
NOTES
1Guaranteed by characterization.
2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: C[9:0]; S[9:0]; Y[9:0]
Control:
P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK
Specifications subject to change without notice.
(VAA = VDD = 2.375 V–2.625 V, VDD_IO = 2.375 V–3.600 V, VREF = 1.235 V, RSET = 760
, RLOAD = 150
,
TMIN to TMAX (0 C to 70 C), unless otherwise noted.)


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