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ADV7300A 数据表(PDF) 6 Page - Analog Devices |
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ADV7300A 数据表(HTML) 6 Page - Analog Devices |
6 / 68 page REV. A –6– ADV7300A/ADV7301A t9 t11 CLKIN_A C9–C0 t10 t12 P_HSYNC, P_VSYNC, P_BLANK Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 CONTROL I/PS Y0 Y1 Y2 Y3 Y4 Y5 Y9–Y0 t14 CONTROL O/PS S_HSYNC, S_VSYNC t13 t 9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME Figure 2. HD 4:2:2 Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV Input Only (Input Mode at Subaddress 01h = 001 or 010) t9 t11 t10 t12 t13 t14 CLKIN_A C9–C0 P_HSYNC, P_VSYNC, P_BLANK CONTROL I/PS Y9–Y0 CONTROL O/PS S_HSYNC, S_VSYNC t 9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME S9–S0 Y0 Y1 Y2 Yxxx Yxxx Cb0 Cb1 Cb2 Cb3 Cbxxx Cbxxx Cr0 Cr1 Cr2 Cr3 Crxxx Crxxx Figure 3. HD 4:4:4 YCrCb Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV Input Only (Input Mode at Subaddress 01h = 001 or 010) |
类似零件编号 - ADV7300A |
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类似说明 - ADV7300A |
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