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AD7918BRU-REEL 数据表(PDF) 4 Page - Analog Devices

部件名 AD7918BRU-REEL
功能描述  8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7918BRU-REEL 数据表(HTML) 4 Page - Analog Devices

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AD7908/AD7918/AD7928
REV. A
Parameter
B Version
1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 50 kHz Sine Wave, fSCLK = 20 MHz
Signal-to-(Noise + Distortion) (SINAD)
2
61
dB min
Signal-to-Noise Ratio (SNR)
2
61
dB min
Total Harmonic Distortion (THD)
2
–72
dB max
Peak Harmonic or Spurious Noise
(SFDR)
2
–74
dB max
Intermodulation Distortion (IMD)
2
fa = 40.1 kHz, fb = 41.5 kHz
Second Order Terms
–90
dB typ
Third Order Terms
–90
dB typ
Aperture Delay
10
ns typ
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation
2
–85
dB typ
fIN = 400 kHz
Full Power Bandwidth
8.2
MHz typ
@ 3 dB
1.6
MHz typ
@ 0.1 dB
DC ACCURACY
2
Resolution
10
Bits
Integral Nonlinearity
±0.5
LSB max
Differential Nonlinearity
±0.5
LSB max
Guaranteed No Missed Codes to 10 Bits
0 V to REFIN Input Range
Straight Binary Output Coding
Offset Error
±2
LSB max
Offset Error Match
±0.2
LSB max
Gain Error
±0.5
LSB max
Gain Error Match
±0.2
LSB max
0 V to 2
REFIN Input Range
–REFIN to +REFIN Biased about REFIN with
Positive Gain Error
±0.5
LSB max
Twos Complement Output Coding
Positive Gain Error Match
±0.2
LSB max
Zero Code Error
±2
LSB max
Zero Code Error Match
±0.2
LSB max
Negative Gain Error
±0.5
LSB max
Negative Gain Error Match
±0.2
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to REFIN
V
RANGE Bit Set to 1
0 to 2
REFIN
V
RANGE Bit Set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
DC Leakage Current
±1
µA max
Input Capacitance
20
pF typ
REFERENCE INPUT
REFIN Input Voltage
2.5
V
±1% Specified Performance
DC Leakage Current
±1
µA max
REFIN Input Impedance
36
k
typ
fSAMPLE = 1 MSPS
LOGIC INPUTS
Input High Voltage, VINH
0.7
VDRIVE
V min
Input Low Voltage, VINL
0.3
VDRIVE
V max
Input Current, IIN
±1
µA max
Typically 10 nA, VIN = 0 V or VDRIVE
Input Capacitance, CIN
3
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
VDRIVE – 0.2
V min
ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V
Output Low Voltage, VOL
0.4
V max
ISINK = 200 µA
Floating-State Leakage Current
±1
µA max
Floating-State Output Capacitance
3
10
pF max
Output Coding
Straight (Natural) Binary
Coding Bit Set to 1
Twos Complement
Coding Bit Set to 0
CONVERSION RATE
Conversion Time
800
ns max
16 SCLK Cycles with SCLK at 20 MHz
Track-and-Hold Acquisition Time
300
ns max
Sine Wave Input
300
ns max
Full-Scale Step Input
Throughput Rate
1
MSPS max
See Serial Interface Section
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless
otherwise noted.)
AD7918–SPECIFICATIONS
–4–


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