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CDCVF2509PW 数据表(PDF) 1 Page - Texas Instruments

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部件名 CDCVF2509PW
功能描述  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Download  16 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDCVF2509PW 数据表(HTML) 1 Page - Texas Instruments

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CLK
AVCC
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
2G
FBIN
1
2
3
4
5
6
7
8
9
10
11
12
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
1G
FBOUT
24
23
22
21
20
19
18
17
16
15
14
13
PW PACKAGE
(TOP VIEW)
NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT
CDCVF2509
www.ti.com
SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Check for Samples: CDCVF2509
1
FEATURES
25-
Ω On-Chip Series Damping Resistors
Use CDCVF2509A (SCAS765) as a
No External RC Network Required
Replacement for This Device
Operates at 3.3 V
Designed to Meet and Exceed PC133
SDRAM Registered DIMM Specification
APPLICATIONS
Rev. 1.1
DRAM Applications
Spread Spectrum Clock Compatible
PLL Based Clock Distributors
Non-PLL Clock Buffer
Operating Frequency 50 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to
166 MHz Is ±125 ps
Jitter (cyc - cyc) at 66 MHz to 166 MHz Is
Typ = 70 ps
Advanced Deep Submicron Process
Results in More Than 40% Lower Power
Consumption Versus Current Generation
PC133 Devices
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
Separate Output Enable for Each Output
Bank
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
DESCRIPTION
The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is
specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at a 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or
disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase
and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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