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CDCVF2509 数据表(PDF) 2 Page - Texas Instruments |
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CDCVF2509 数据表(HTML) 2 Page - Texas Instruments |
2 / 16 page 1Y2 1Y1 1Y0 PLL FBIN AVCC 2G CLK 1G 2Y2 2Y1 2Y0 2Y3 FBOUT 1Y3 1Y4 11 14 24 13 23 3 4 5 8 9 21 20 17 16 12 NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED Because it is based on PLL circuitry, the CDCVF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground. The CDCVF2509A is characterized for operation from 0°C to 85°C. For application information, see application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (SCAA039). FUNCTION TABLE INPUTS OUTPUTS 1G 2G CLK 1Y (0:4) 2Y (0:3) FBOUT X X L L L L L L H L L H L H H L H H H L H H L H H H H H H H FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 |
类似零件编号 - CDCVF2509_15 |
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类似说明 - CDCVF2509_15 |
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