CDCM6208V2GRGZR datasheet(11/88 Pages) TI1

部件名	CDCM6208V2GRGZR

功能描述	CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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制造商	TI1 [Texas Instruments]

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CDCM6208V2G

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SNAS682 – MARCH 2016

Product Folder Links: CDCM6208V2G

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8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V;

TA = –40°C to 85°C (Output load capacitance 10 pF unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

Output High Voltage

Status 1, Status 0, and SDO only;

SDA is open drain and relies on

external pullup for high output; IOH =

1 mA

0.8 x

DVDD

V

VOL

Output Low Voltage

IOL = 1 mA

0.2 x

DVDD

V

Vslew

Output slew rate

30% - 70%

0.5

V/ns

IOZH

3-stat Output High Current

DVDD = 3.465 V, VIH = 3.465 V

5

µA

IOZL

3-stat Output Low Current

DVDD = 3.465 V, VIL = 0 V

-5

µA

tLOS

Status Loss of Signal Detection

Time

LOS_REFfvco

1

2

1/f PFD

tLOCK

Status PLL Lock Detection Time

Detect lock

2304

1/f PFD

Detect unlock

512

8.13 PLL Characteristics

VDD_PLLx, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fVCO

VCO Frequency Range

2.39

2.55

GHz

KVCO

VCO Gain

2.39 GHz

178

MHz/V

2.50 GHz

204

2.55 GHz

213

fPFD

PFD Input Frequency

0.008

100

MHz

ICP-L

High Impedance Mode Charge

Pump Leakage

±700

nA

fFOM

Estimated PLL Figure of Merit

(FOM)

Measured in-band phase noise at

the VCO output minus 20log(N-

divider) at the flat region

–224

dBc/Hz

tSTARTUP

Startup time (see Figure 41 )

Power supply ramp time of 1ms from

0 V to 1.7 V, final frequency

accuracy of 10 ppm, fPFD = 25 MHz,

CPDN_to_GND = 22nF

w/ PRI input signal

12.8

ms

w/ NDK 25 MHz crystal

12.85

ms

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