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CDCE421RGETG4 数据表(PDF) 6 Page - Texas Instruments

部件名 CDCE421RGETG4
功能描述  Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator
Download  24 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDCE421RGETG4 数据表(HTML) 6 Page - Texas Instruments

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Enter Programming Mode
SDATA
CE
0
t
2
DATA
0
1
1
0
0
SDATA
DELAYED
t
1
t
f
t
5
t
4
t
r
T0042-05
t
3
t
7
EEPROM PROGRAMMING
CDCE421
SCAS842B – APRIL 2007 – REVISED JANUARY 2009..................................................................................................................................................... www.ti.com
Figure 3 shows the timing behavior of data to be written into SDATA. The sequence shown is 00 1100. If the high
period is as short as t1, this is interpreted as 0. If the high period is as long as t3, this is interpreted as a 1. This
behavior is achieved by shifting the incoming signal SDATA by time t5 into signal SDATA_DELAYED. As can be
seen in Figure 3, SDATA_DELAYED can be used to latch (or strobe) SDATA. The timing specifications for t1–t7,
tr, and tf are shown in Figure 3.
MIN
TYP
MAX
UNIT
fSDATACLK
Repeat frequency of programming
60
70
80
kHz
t1
LOW signal: high-pulse duration
0.2 t
ms
t2
LOW signal: low-pulse duration while entering programming sequence
0.8 t
ms
t2
LOW signal: low-pulse duration while programming bits
0.8 t
ms
t3
HIGH signal: high-pulse duration
0.8 t
ms
t4
HIGH signal: low-pulse duration while entering programming sequence
0.2 t
ms
t4
HIGH signal: low-pulse duration while programming bits
0.2 t
ms
Time-out during Entering Programming Mode and Enter Read Back Mode.
t6
High-pulse or low-pulse duration each must be less than this time; otherwise,
16
µs
time-out will result.
t7
CE-high time before first SDATA can be clocked in
3 t
ms
tr and tf
Rise Time and Fall Time
2
ns
t = 1 / fSDATACLK
Figure 3. SDATA/CE Timing
Load all the registers in RAM by writing Word0 through Word5, and after going back to State 2, then going to
State 3 (programming EEPROM, no locking) or State 4 (programming EEPROM with locking), the contents of
Word0–Word5 are saved in the EEPROM. Wait 10 ms in State 3 or State 4 when programming the EEPROM
before moving to State 2 (the idle state).
NOTE:
When writing to the device for functionality testing and verification via the serial bus,
only the RAM is being accessed.
6
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): CDCE421


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