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CDCEL913IPWRQ1 数据表(PDF) 3 Page - Texas Instruments |
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CDCEL913IPWRQ1 数据表(HTML) 3 Page - Texas Instruments |
3 / 27 page EEPROM Xin/CLK Xout VDD GND InputClock Vctr S0 Programming and SDA/SCL Register Y2 Y1 Y3 LV CMOS Pdiv1 10-Bit LV CMOS Pdiv3 7-Bit Pdiv2 7-Bit PLL Bypass LV CMOS PLL 1 withSSC S1/SDA S2/SCL VCXO XO LVCMOS VDDOUT CDCE913-Q1 CDCEL913-Q1 www.ti.com SCAS918A – JUNE 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT VDD Supply voltage range –0.5 to 2.5 V VI Input voltage range(2) (3) –0.5 to VDD + 0.5 V VO Output voltage range(2) –0.5 to VDD + 0.5 V II Input current (VI < 0, VI > VDD) 20 mA IO Continuous output current 50 mA Tstg Storage temperature range –65 to 150 °C TJ Maximum junction temperature 125 °C Human-body model 2500 ESD V rating Charged-device model (4) 500 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table. (4) Charged-device model ESD rating for corner pins is 750 V. THERMAL INFORMATION CDCE913-Q1, CDCEL913- Q1 THERMAL METRIC(1) UNIT PW 14 PINS θJA Junction-to-ambient thermal resistance(2) 110.6 °CW θJCtop Junction-to-case (top) thermal resistance(3) 35.4 °CW θJB Junction-to-board thermal resistance(4) 53.6 °CW ψJT Junction-to-top characterization parameter(5) 2.1 °CW (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CDCE913-Q1 CDCEL913-Q1 |
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