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CDC5801ADBQR 数据表(PDF) 10 Page - Texas Instruments

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部件名 CDC5801ADBQR
功能描述  Low Jitter Clock Multiplier
Download  18 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDC5801ADBQR 数据表(HTML) 10 Page - Texas Instruments

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CDC5801A
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
state transition latency specifications
PARAMETER
FROM
TO
TEST
CONDITIONS
MIN
TYP†
MAX
UNIT
t(powerup)
Delay time, PWRDNB
↑ to CLKOUT/
CLKOUTB output settled (excluding
t(DISTLOCK))
Powerdown
Normal
See Figure 6
3
ms
t(powerup)
Delay time, PWRDNB
↑ to internal PLL and
clock are on and settled
Powerdown
Normal
See Figure 6
3
ms
t(VDDpowerup)
Delay time, power up to CLKOUT/CLKOUTB
output settled
VDD
Normal
See Figure 6
3
ms
t(VDDpowerup)
Delay time, power up to internal PLL and
clock are on and settled
VDD
Normal
See Figure 6
3
ms
t(MULT)
MULT0 and MULT1 change to CLKOUT/
CLKOUTB output resettled (excluding
t(DISTLOCK))
Normal
Normal
See Figure 7
1
ms
t(CLKON)
STOPB
↑ to CLKOUT/CLKOUTB glitch-free
clock edges
CLK Stop
Normal
See Figure 8
10
ns
t(CLKSETL)
STOPB
↑ to CLKOUT/CLKOUTB output
settled to within 50 ps of the phase before
STOPB was disabled
CLK Stop
Normal
See Figure 8
20
cycles
t(CLKOFF)
STOPB
↓ to CLKOUT/CLKOUTB output dis-
abled
Normal
CLK
Stop
See Figure 8
5
ns
t(powerdown)
Delay time, PWRDNB
↓ to the device in the
power-down mode
Normal
Power−
down
See Figure 6
1
ms
t(STOP)
Maximum time in CLKSTOP (STOPB = 0)
before reentering normal mode (STOPB = 1)
STOPB
Normal
See Figure 8
100
µs
t(ON)
Minimum time in normal mode (STOPB = 1)
before reentering CLKSTOP (STOPB = 0)
Normal
CLK
stop
See Figure 8
100
ms
† All typical values are at VDD = 3.3 V, TA = 25°C.
PARAMETER MEASUREMENT INFORMATION
50
CLKOUTB
CLKOUT
10 pF
50
VCM
Figure 1. Test Load and Voltage Definitions (VO(STOP), VOX, VOH, VOL)


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