CDC2516

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS579C − OCTOBER 1996 − REVISED DECEMBER 2004

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POST OFFICE BOX 655303

this Device

Synchronous DRAM Applications

of Four Outputs

Bank

Synchronize the Outputs to the Clock Input

Small-Outline Package

description

The CDC2516 is a high-performance, low-skew,

low-jitter, phase-lock loop (PLL) clock driver. It

uses a PLL to precisely align, in both frequency

and phase, the feedback output (FBOUT) to the

clock (CLK) input signal. It is specifically designed

for use with synchronous DRAMs. The CDC2516

series-damping resistors that make it ideal for

driving point-to-point loads.

Four banks of four outputs provide 16 low-skew,

low-jitter copies of the input clock. Output signal

duty

cycles

are

adjusted

to

50

percent,

independent of the duty cycle at the input clock.

Each bank of outputs can be enabled or disabled

separately via the 1G, 2G, 3G, and 4G control

inputs. When the G inputs are high, the outputs

switch in phase and frequency with CLK; when the

G inputs are low, the outputs are disabled to the

logic-low state.

Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application

of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or

The CDC2516 is characterized for operation from 0

°C to 70°C.

Copyright

 2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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1Y0

1Y1

GND

GND

1Y2

1Y3

1G

GND

CLK

AGND

AGND

GND

2G

2Y0

2Y1

GND

GND

2Y2

2Y3

4Y0

4Y1

GND

GND

4Y2

4Y3

4G

GND

FBIN

AGND

FBOUT

GND

3G

3Y0

3Y1

GND

GND

3Y2

3Y3

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