CDC2510

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS597B − DECEMBER 1997 − REVISED DECEMBER 2004

5

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

fclock

Clock frequency

25

125

MHz

Input clock duty cycle

40%

60%

Stabilization time†

1

ms

† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,

and jitter parameters given in the switching characteristics table are not applicable.

switching characteristics over recommended ranges of supply voltage and operating free-air

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.165 V

VCC = 3.3 V

± 0.3 V

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

tphase error,

reference

(see Figure 3)

66 MHz < CLKIN

↑ < 100 MHz

FBIN

↑

−0.7...0.1

ns

tphase error

− jitter

(see Note 6)

CLKIN

↑ = 100 MHz

FBIN

↑

−500

−50

− 310

ps

tsk(o)§

Any Y or FBOUT

Any Y or FBOUT

200

ps

Jitter(pk-pk)

F(clkin > 66 MHz)

Any Y or FBOUT

−100

100

ps

Duty cycle

reference

(see Figure 4)

Any Y or FBOUT

43%

55%

tr

Any Y or FBOUT

1.3

1.9

0.8

2.1

ns

tf

Any Y or FBOUT

1.7

2.3

1.2

2.5

ns

‡ These parameters are not production tested.

§ The tsk(o) specification is only valid for equal loading of all outputs.

NOTES:

5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

6. Phase error does not include jitter. The total phase error is − 600 ps to 50 ps for the 5% VCC range.