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DAC60004IPW 数据表(PDF) 3 Page - Texas Instruments |
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DAC60004IPW 数据表(HTML) 3 Page - Texas Instruments |
3 / 38 page Thermal Pad 1 LDAC 14 SCLK 2 SYNC 13 SDIN 3 VDD 12 GND 4 VOUTA 11 VOUTB 5 VOUTC 10 VOUTD 6 POR 9 CLR 7 REFIN 8 SDO Thermal Pad 1 LDAC 14 SCLK 2 SYNC 13 SDIN 3 VDD 12 GND 4 VOUTA 11 VOUTB 5 VOUTC 10 VOUTD 6 POR 9 CLR 7 REFIN 8 SDO 3 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 5 Device Comparison Table DEVICE RESOLUTION DAC80004 16 DAC70004 14 DAC60004 12 6 Pin Configuration and Functions 14-Pin VSON DMD Package Top View 14-Pin TSSOP PW Package Top View Pin Functions PIN I/O DESCRIPTION NAME NUMBER CLR 9 Digital Input Clear DAC pin, falling edge sensitive GND 12 Power Ground LDAC 1 Digital Input Load DAC pin, active low POR 6 Digital Input Power-on-reset configuration, Connecting the POR pin to GND powers up all four DACs to zero scale. Connecting this pin to VDD powers up all four DACs to midscale. REFIN 7 Analog Input Voltage reference input for all channels SCLK 14 Digital Input Serial interface shift clock SDIN 13 Digital Input Serial interface digital input SDO 8 Digital Output Serial interface digital output for readback and daisy chaining SYNC 2 Digital Input Serial interface synchronization, active low VDD 3 Power Positive power supply (2.7 V to 5.5 V) VOUTA 4 Analog Output DAC A output VOUTB 11 Analog Output DAC B output VOUTC 5 Analog Output DAC C output VOUTD 10 Analog Output DAC D output |
类似零件编号 - DAC60004IPW |
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类似说明 - DAC60004IPW |
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