DAC7553IRGTRG4 datasheet(5/26 Pages) TI1

部件名	DAC7553IRGTRG4

功能描述	12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

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制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

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TIMING CHARACTERISTICS

(1) (2)

SCLK

SYNC

SDIN

D15

D14

D13

D12

D11

D1

D0

D15

t8

t4

t3

t2

t1

t7

t6

t5

D0

t9

Input Word n

Input Word n+1

Undefined

D15

D14

D0

Input Word n

t10

SDO

CLR

DAC7553

SLAS477 – SEPTEMBER 2005

V

DD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VDD = 2.7 V to 3.6 V

20

t1(3)

SCLK cycle time

ns

VDD = 3.6 V to 5.5 V

20

VDD = 2.7 V to 3.6 V

10

t2

SCLK HIGH time

ns

VDD = 3.6 V to 5.5 V

10

VDD = 2.7 V to 3.6 V

10

t3

SCLK LOW time

ns

VDD = 3.6 V to 5.5 V

10

VDD = 2.7 V to 3.6 V

4

SYNC falling edge to SCLK falling edge setup

t4

ns

time

VDD = 3.6 V to 5.5 V

4

VDD = 2.7 V to 3.6 V

5

t5

Data setup time

ns

VDD = 3.6 V to 5.5 V

5

VDD = 2.7 V to 3.6 V

4.5

t6

Data hold time

ns

VDD = 3.6 V to 5.5 V

4.5

VDD = 2.7 V to 3.6 V

0

t7

SCLK falling edge to SYNC rising edge

ns

VDD = 3.6 V to 5.5 V

0

VDD = 2.7 V to 3.6 V

20

t8

Minimum SYNC HIGH time

ns

VDD = 3.6 V to 5.5 V

20

VDD = 2.7 V to 3.6 V

10

t9

SCLK falling edge to SDO valid

ns

VDD = 3.6 V to 5.5 V

10

VDD = 2.7 V to 3.6 V

10

t10

CLR pulse width low

ns

VDD = 3.6 V to 5.5 V

10

(1)

All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

(2)

See Serial Write Operation timing diagram Figure 1.

(3)

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

Figure 1. Serial Write Operation

5

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