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DM74LS165N 数据表(PDF) 1 Page - National Semiconductor (TI) |
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DM74LS165N 数据表(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF6399 May 1992 DM54LS165DM74LS165 8-Bit Parallel InSerial Output Shift Registers General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked Parallel-in ac- cess is made available by eight individual direct data inputs which are enabled by a low level at the shiftload input These registers also feature gated clock inputs and comple- mentary outputs from the eighth bit Clocking is accomplished through a 2-input NOR gate per- mitting one input to be used as a clock-inhibit function Hold- ing either of the clock inputs high inhibits clocking and hold- ing either clock input low with the load input high enables the other clock input The clock-inhibit input should be changed to the high level only while the clock input is high Parallel loading is inhibited as long as the load input is high Data at the parallel inputs are loaded directly into the regis- ter on a high-to-low transition of the shiftload input regard- less of the logic levels on the clock clock inhibit or serial inputs Features Y Complementary outputs Y Direct overriding (data) inputs Y Gated clock inputs Y Parallel-to-serial data conversion Y Typical frequency 35 MHz Y Typical power dissipation 105 mW Connection Diagram Dual-In-Line Package TLF6399 – 1 Order Number DM54LS165J DM54LS165W DM74LS165WM or DM74LS165N See NS Package Number J16A M16B N16E or W16A Function Table Inputs Internal Shift Clock Clock Serial Parallel Outputs Output Load Inhibit AH QA QB QH L X X X ah a b h HL L X X QA0 QB0 QH0 HL u HX H QAn QGn HL u LX L QAn QGn HH X X X QA0 QB0 QH0 H e High Level (steady state) L e Low Level (steady state) X e Don’t Care (any input including transitions) u e Transition from low-to-high level ah e The level of steady-state input at inputs A through H respectively QA0 QB0 QH0 e The level of QA QB orQH respectively before the indicated steady-state input conditions were established QAn QGn e The level of QA or QG respectively before the most recent u transition of the clock C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
类似零件编号 - DM74LS165N |
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类似说明 - DM74LS165N |
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