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DM54161 数据表(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 DM54161
功能描述  Synchronous 4-Bit Counters
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

DM54161 数据表(HTML) 3 Page - National Semiconductor (TI)

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Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
IOS
Short Circuit
VCC e Max
DM54
b
20
b
57
mA
Output Current
(Note 2)
DM74
b
20
b
57
ICCH
Supply Current
VCC e Max
DM54
85
mA
with Outputs High
(Note 3)
DM74
59
94
ICCL
Supply Current
VCC e Max
DM54
91
mA
with Outputs Low
(Note 4)
DM74
63
101
Note 1
All typicals are at VCC e 5V TA e 25 C
Note 2
Not more than one output should be shorted at a time
Note 3
ICCH is measured with the LOAD high then again with the LOAD low with all inputs high and all outputs open
Note 4
ICCL is measured with the CLOCK high then again with the CLOCK input low with all inputs low and all outputs open
Note 5
Applies to 163 which has synchronous clear inputs
Note 6
TA e 25 C and VCC e 5V
Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
RL e 400X CL e 15 pF
Units
To (Output)
Min
Max
fMAX
Maximum Clock
25
MHz
Frequency
tPLH
Propagation Delay Time
Clock to
35
ns
Low to High Level Output
Ripple Carry
tPHL
Propagation Delay Time
Clock to
35
ns
High to Low Level Output
Ripple Carry
tPLH
Propagation Delay Time
Clock
20
ns
Low to High Level Output
(Load High) to Q
tPHL
Propagation Delay Time
Clock
23
ns
High to Low Level Output
(Load High) to Q
tPLH
Propagation Delay Time
Clock
25
ns
Low to High Level Output
(Load Low) to Q
tPHL
Propagation Delay Time
Clock
29
ns
High to Low Level Output
(Load Low) to Q
tPLH
Propagation Delay Time
Enable T to
16
ns
Low to High Level Output
Ripple Carry
tPHL
Propagation Delay Time
Enable T to
16
ns
High to Low Level Output
Ripple Carry
tPHL
Propagation Delay Time
Clear (Note 7)
38
ns
High to Low Level Output
to Q
Note 7
Propagation delay for clearing is measured from the clear input for the 161 or from the clock input transition for the 163
3


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