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GS70328SJ-8T 数据表(PDF) 6 Page - GSI Technology |
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GS70328SJ-8T 数据表(HTML) 6 Page - GSI Technology |
6 / 11 page GS70328SJ/TS Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.11 11/2004 6/11 © 1999, GSI Technology Read Cycle 2: WE = VIH * These parameters are sampled and are not 100% tested Write Cycle Parameter Symbol -7 -8 -10 -12 -15 Unit Min Max Min Max Min Max Min Max Min Max Write cycle time tWC 7 — 8 — 10 — 12 — 15 — ns Address valid to end of write tAW 5 — 5.5 — 7 — 10 — 13 — ns Chip enable to end of write tCW 5 — 5.5 — 7 — 10 — 13 — ns Data set up time tDW 3.5 — 4 — 5 — 7 — 10 — ns Data hold time tDH 0 — 0 — 0 — 0 — 0 — ns Write pulse width tWP 5 — 5.5 — 7 — 10 — 13 — ns Address set up time tAS 0 — 0 — 0 — 0 — 0 — ns Write recovery time (WE) tWR 0—0—0— 0 — 0 — ns Write recovery time (CE) tWR1 0 —0—0— 0 — 0 — ns Output Low Z from end of write tWLZ* 2—2—2— 3 — 3 — ns Write to output in High Z tWHZ* —3— 3.5 —4 — 5 — 5 ns tAA tRC Address tAC tLZ tOE tOLZ CE OE Data Out tHZ tOHZ DATA VALID High impedance |
类似零件编号 - GS70328SJ-8T |
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类似说明 - GS70328SJ-8T |
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