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FM25V02A-G 数据表(PDF) 6 Page - Cypress Semiconductor |
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FM25V02A-G 数据表(HTML) 6 Page - Cypress Semiconductor |
6 / 23 page FM25V02A Document Number: 001-90865 Rev. *F Page 6 of 23 The device detects the SPI mode from the status of the SCK pin when the device is selected by bringing the CS pin LOW. If the SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if the SCK pin is HIGH, it works in SPI Mode 3. Power-Up to First Access The FM25V02A is not accessible for a tPU time after power-up. Users must comply with the timing parameter tPU, which is the minimum time from VDD (min) to the first CS LOW. Command Structure There are nine commands, called opcodes, that can be issued by the bus master to the FM25V02A. They are listed in Table 1. These opcodes control the functions performed by the memory. WREN - Set Write Enable Latch The FM25V02A will power up with writes disabled. The WREN command must be issued before any write operation. Sending the WREN opcode allows the user to issue subsequent opcodes for write operations. These include writing the Status Register (WRSR) and writing the memory (WRITE). Sending the WREN opcode causes the internal Write Enable Latch to be set. A flag bit in the Status Register, called WEL, indicates the state of the latch. WEL = ‘1’ indicates that writes are permitted. Attempting to write the WEL bit in the Status Register has no effect on the state of this bit - only the WREN opcode can set this bit. The WEL bit will be automatically cleared on the rising edge of CS following a WRDI, a WRSR, or a WRITE operation. This prevents further writes to the Status Register or the F-RAM array without another WREN command. Figure 7 illustrates the WREN command bus configuration. WRDI - Reset Write Enable Latch The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the Status Register and verifying that WEL is equal to ‘0’. Figure 8 illustrates the WRDI command bus configuration. Figure 5. SPI Mode 0 Figure 6. SPI Mode 3 Table 1. Opcode Commands Name Description Opcode WREN Set write enable latch 0000 0110b WRDI Reset write enable latch 0000 0100b RDSR Read Status Register 0000 0101b WRSR Write Status Register 0000 0001b READ Read memory data 0000 0011b FSTRD Fast read memory data 0000 1011b WRITE Write memory data 0000 0010b SLEEP Enter sleep mode 1011 1001b RDID Read device ID 1001 1111b Reserved Reserved 1100 0011b 1100 0010b 0101 1010b 0101 1011b LSB MSB 7 654 321 0 CS SCK SI 01 2 3 4 5 67 CS SCK SI 7 654 32 10 LSB MSB 01 2 3 4 5 67 Figure 7. WREN Bus Configuration Figure 8. WRDI Bus Configuration 0 0 0 0 0 1 1 0 CS SCK SI SO HI-Z 0 1 2 3 4 5 6 7 0 0 0 CS SCK SI SO HI-Z 0 1 2 3 4 5 6 7 0 0 00 1 |
类似零件编号 - FM25V02A-G |
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类似说明 - FM25V02A-G |
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