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FM24V02A-G 数据表(PDF) 11 Page - Cypress Semiconductor

部件名 FM24V02A-G
功能描述  256-Kbit (32K 횞 8) Serial (I2C) F-RAM
Download  19 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

FM24V02A-G 数据表(HTML) 11 Page - Cypress Semiconductor

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FM24V02A
Document Number: 001-90839 Rev. *G
Page 11 of 19
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55
C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V
Input voltage* ......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
DC voltage applied to outputs
in HI-Z state ........................................ –0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VDD + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount lead soldering
temperature (3 seconds) ......................................... +260
C
Electrostatic discharge voltage
Human Body Model (JEDEC Std JESD22-A114-B) .............. 2 kV
Charged Device Model (JEDEC Std JESD22-C101-A) ........ 500 V
Latch-up current .................................................... > 140 mA
* Exception: The “VIN < VDD + 1.0 V” restriction does not apply
to the SCL and SDA inputs.
Operating Range
Range
Ambient Temperature (TA)
VDD
Industrial
–40
C to +85 C
2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ [2]
Max
Unit
VDD
Power supply
2.0
3.3
3.6
V
IDD
Average VDD current
SCL toggling
between
VDD – 0.2 V and VSS,
other inputs VSS or
VDD – 0.2 V.
fSCL = 100 kHz
175
A
fSCL = 1 MHz
400
A
fSCL = 3.4 MHz
1000
A
ISB
VDD standby current
SCL = SDA = VDD. All other inputs VSS or
VDD. Stop command issued.
–90
150
A
IZZ
Sleep mode current
SCL = SDA = VDD. All other inputs VSS or
VDD. Stop command issued.
–5
8
A
ILI
Input leakage current
(Except WP and A2-A0)
VSS < VIN < VDD
–1
+1
A
Input leakage current
(for WP and A2-A0)
–1
+100
A
ILO
Output leakage current
VSS < VOUT < VDD
–1
+1
A
VIH
Input HIGH voltage (SDL, SDA)
0.7 × VDD
–VDD(max)+
0.3
V
Input HIGH voltage (WP, A2-A0)
0.7 × VDD
–VDD + 0.3
V
VIL
Input LOW voltage
– 0.3
0.3 × VDD
V
VOL[3]
Output LOW voltage
IOL = 3 mA
0.4
V
IOL = 6 mA
0.6
V
Rin[4]
Input resistance (WP, A2-A0)
For VIN = VIL(Max)
50
k
For VIN = VIH(Min)
1–
M
Vhys[5]
Hysteresis of Schmitt Trigger
inputs
fSCL = 100 kHz,
400 kHz, 1 MHz
0.05 × VDD
––
V
fSCL = 3.4 MHz
0.06 × VDD
––
V
Notes
2. Typical values are at 25 °C, VDD = VDD(typ). Not 100% tested.
3. The FM24V02A does not meet the NXP I2C specification in the Fast-mode Plus (Fm+, 1 MHz) for IOL of 20 mA at a VOL of 0.4 V.
4. The input pull-down circuit is strong (50 k
) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH.
5. The FM24V02A does not meet the NXP I2C specification in the High Speed Mode (Hs-mode, 3.4 MHz) for Vhys of 0.1 × VDD.


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