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AD7172-4 数据表(PDF) 7 Page - Analog Devices |
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AD7172-4 数据表(HTML) 7 Page - Analog Devices |
7 / 61 page Data Sheet AD7172-4 Rev. A | Page 7 of 61 TIMING CHARACTERISTICS IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted. Table 2. Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments1, 2 SCLK t3 25 ns min SCLK high pulse width t4 25 ns min SCLK low pulse width READ OPERATION t1 0 ns min CS falling edge to DOUT/RDY active time 15 ns max IOVDD = 4.75 V to 5.5 V 40 ns max IOVDD = 2 V to 3.6 V t23 0 ns min SCLK active edge to data valid delay4 12.5 ns max IOVDD = 4.75 V to 5.5 V 25 ns max IOVDD = 2 V to 3.6 V t5 2.5 ns min Bus relinquish time after CS inactive edge 20 ns max t6 0 ns min SCLK inactive edge to CS inactive edge t75 10 ns min SCLK inactive edge to DOUT/RDY high/low WRITE OPERATION t8 0 ns min CS falling edge to SCLK active edge setup time4 t9 8 ns min Data valid to SCLK edge setup time t10 8 ns min Data valid to SCLK edge hold time t11 5 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. 2 See Figure 2 and Figure 3. 3 This parameter is defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. TIMING DIAGRAMS t2 t3 t4 t1 t6 t5 t7 CS (I) DOUT/RDY (O) SCLK (I) I = INPUT, O = OUTPUT MSB LSB Figure 2. Read Cycle Timing Diagram I = INPUT, O = OUTPUT CS (I) SCLK (I) DIN (I) MSB LSB t8 t9 t10 t11 Figure 3. Write Cycle Timing Diagram |
类似零件编号 - AD7172-4 |
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类似说明 - AD7172-4 |
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