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ADC1038CIWM 数据表(PDF) 8 Page - National Semiconductor (TI) |
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ADC1038CIWM 数据表(HTML) 8 Page - National Semiconductor (TI) |
8 / 13 page ADC1038 Functional Block Diagram 1.0 Pin Descriptions C CLK The clock applied to this input controls the suc- cessive approximation conversion time interval. The clock frequency applied to this input can be between 700 kHz and 4 MHz. S CLK The serial data clock input. The clock applied to this input controls the rate at which the serial data exchange occurs and the analog sampling time available to acquire an analog input volt- age. The rising edge loads the information on the DI pin into the multiplexer address shift reg- ister (address register). This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts the data resulting from the previous A/D conversion out on DO. CS and OE enable or disable the above functions. DI The serial data input pin. The data applied to this pin is shifted by S CLK into the multiplexer address register. The first 3 bits of data (A0–A2) are the MUX channel address (see the Multi- plexer Address/Channel Assignment tables). The fourth bit (R/L ) determines the data format of the conversion result in the conversion to be www.national.com 8 |
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