Functional Description

The ADC10030 maintains excellent dynamic performance

for input signals up to and exceeding half the clock fre-

quency. The use of an internal sample-and-hold amplifier

(SHA) enables sustained dynamic performance for signals of

input frequency beyond the clock rate, lowers the converter’s

input capacitance and reduces the number of external com-

ponents required.

The analog signal at V

by V

30 MSPS. Input voltages below V

put word to consist of all zeroes. Input voltages above

V

V

range of 1.7V to 2.8V. V

1.0V more positive than V

Data is acquired at the falling edge of the clock and the digi-

tal equivalent of that data is available at the digital outputs

2.0 clock cycles plus t

long as the clock signal is present at pin 9 and the PD pin is

low. The Output Enable pin (OE), when low, enables the out-

put pins. The digital outputs are in the high impedance state

when the OE pin or the PD pin is high.

Applications Information

1.0 THE ANALOG INPUT

The analog input of the ADC10030 is a switch (transmission

gate) followed by a switched capacitor amplifier. The capaci-

tance seen at the input changes with the clock level, appear-

ing as about 3 pF when the clock is low, and about 5 pF

when the clock is high. This small change in capacitance can

be reasonably assumed to be a fixed capacitance. Care

should be taken to avoid driving the input beyond the supply

rails, even momentarily, as during power-up.

The CLC409 has been found to be a good device to drive the

ADC10030 because of its wide bandwidth, low distortion and

minimal Differential Gain and Differential Phase. The

CLC409 performs best with a feedback resistor of about

100

Ω.

Care should be taken to keep digital noise out of the analog

input circuitry to maintain highest noise performance.

2.0 REFERENCE INPUTS

These refer to the internal voltage across the reference ladder and are,

Figure 4 shows a simple reference biasing scheme with

minimal components. While this circuit might suffice for

some applications, it does suffer from thermal drift because

the external will have a different temperature coefficient than

the on-chip resistors. Also, the on-chip resistors, while well

matched to each other, will have a large tolerance compared

with any external resistors, causing the value of V

V

The V

AGND with 10 µF tantalum or electrolytic capacitors and

0.1 µF ceramic capacitors.

The circuit of

Figure 5 is an improvement over the circuit of

Figure 4 in that the positive end of the reference ladder is de-

fined with a reference voltage. This reduces problems of

high reference variability and thermal drift.

In addition to the usual V

puts, the ADC10030 has two sense outputs for precision

control of the ladder voltages. These sense outputs (V

S and V

tween the source of the reference voltages and the ends of

the reference ladder itself.

With the addition of two op-amps, the voltages at the top and

bottom of the reference ladder can be forced to the exact

value desired, as shown in

Figure 6.

DS101064-17

FIGURE 2. AC Test Circuit

DS101064-16

FIGURE 3. t

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