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UC1846-SP 数据表(PDF) 3 Page - Texas Instruments |
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UC1846-SP 数据表(HTML) 3 Page - Texas Instruments |
3 / 29 page 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 B Out V C NC Gnd A Out C/S– C/S+ NC E/A+ E/A– 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C/L SS C/S– C/S+ E/A+ E/A– Comp C T Shutdown V IN B Out V C Gnd A Out Sync R T V REF UC1846-SP www.ti.com SLUS871C – JANUARY 2009 – REVISED OCTOBER 2015 5 Pin Configuration and Functions FK Package J or W Package 20-Pin LCCC 16-Pin CDIP or CFP Top View Top View Pin Functions PIN I/O DESCRIPTION NAME CDIP or CFP LCCC CL SS 1 2 I Current limit/Soft start VREF 2 3 O 5.1-V internally generated reference CS- 3 4 I Inverting input of current sense operational amplifier CS+ 4 5 I Non-Inverting input of current sense operational amplifier EA+ 5 7 I Non-Inverting input of error amplifier EA- 6 8 I Inverting input of error amplifier COMP 7 9 O Output of error amplifier Timing capacitance. Capacitor connected from CT to ground is charged via CT 8 10 I current established by RT pin via current mirror. Output Pulse dead time is determined by the size of the capacitor during capacitor discharge time. Determines oscillator frequency. VREF sources thru RT to create a current RT 9 12 I which is mirrored to CT pin. Sync pin is an output under normal operation when RT is above 4.1-V Sync SYNC 10 13 I/O output high. Sync pin is an input when RT pin is high and CT pin tied low. AOUT 11 14 O Output driver (source/sink) GND 12 15 — Ground connection VC 13 17 I Gate drive collector supply voltage. Decouple with capacitor. BOUT 14 18 O Output driver (source/sink) VIN 15 19 I Input voltage decouple with capacitor SHUTDOWN 16 20 I Shutdown threshold 1 V. Voltage above threshold latches off oscillator. NC — 1, 6, 11 — No connect Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: UC1846-SP |
类似零件编号 - UC1846-SP_15 |
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类似说明 - UC1846-SP_15 |
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