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LM3262TME 数据表(PDF) 6 Page - Texas Instruments |
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LM3262TME 数据表(HTML) 6 Page - Texas Instruments |
6 / 41 page LM3262 SNVS875O – AUGUST 2012 – REVISED DECEMBER 2015 www.ti.com 6.6 System Characteristics The following parameters are specified by design and verifications providing the component values in the Typical Application Circuit are used. These parameters are not verified by production testing. Minimum (MIN) and maximum (MAX) values are specified over the ambient temperature range TA = −30°C ≤ TA ≤ +90°C and over the VIN range = 2.5 V to 5.5 V, unless otherwise specified; L = 0.5 μH, DCR = 50 mΩ, CIN = 10 μF, 6.3 V, 0402 (1005), COUT = 4.7 μF, 6.3 V, 0402 (1005). For bench evaluation, see (1). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D Maximum duty cycle MODE = LOW 100% 2.5 V ≤ VIN ≤ 5.5 V 800 2.5 × VCON ≤ VIN – 285 mV Maximum output current IOUT mA 2.5 V ≤ VIN ≤ 5.5 V capability 2.5 × VCON ≤ VIN – 165 mV, bypass 1000 mode –3% 3% VOUT linearity VCON = 0.16 V to 1.44 V 0 mA ≤ IOUT ≤ 800 mA (2) –50 50 mV VIN = 3.8 V, VOUT = 0.8 V 71% IOUT = 10 mA, ECO mode VIN = 3.8 V, VOUT = 2.5 V η Efficiency 92% IOUT = 200 mA, PWM mode VIN = 3.8 V, VOUT = 3.4 V 93% IOUT = 500 mA, PWM mode VIN = 3.6 V to 4.2 V, TR = TF = 10 µs, LINE_tr Line transient response 50 mVpk IOUT = 100 mA, VOUT = 0.8 V VIN = 3.1/3.6/4.5 V, VOUT = 0.8 V LOAD_tr Load transient response IOUT = 50 mA to 150 mA 50 mVpk TR = TF = 10 µs, (1) When the LM3262 device is being evaluated apart from a normal system design or on a PCB other than the TI LM3262 evaluation module, user should ensure that a 50-µF to 100- μF ceramic input capacitor is added to the PCB to keep input voltage from sagging during rapid load transitions. (2) Linearity limits are ±3% or ±50 mV, whichever is larger. VOUT is monotonic in nature with respect to VCON input. 6.7 Timing Requirements MIN NOM MAX UNIT VOUT rise time VCON change to 90%; VIN = 3.7 V, VOUT = 1.4 V to 3.4 V 5 µs 0.1 µs < VCON_TR < 1 µs, RL = 12 Ω TVCON_TR VOUT fall time VCON change to 10%; VIN = 3.7 V, VOUT = 3.4 V to 1.4 V 5 µs 0.1 µs < VCON_TR < 1 µs, RL = 12 Ω Turnon time (time for output to reach 95% final value after Enable low-to- high transition) TON 50 µs EN = low-to-high, VIN = 4.2 V , VOUT = 3.4 V IOUT ≤ 1 mA, COUT = 4.7 µF TBP, NEG Auto bypass detect negative threshold delay time(1) 10 µs TBP, POS Auto bypass detect positive threshold delay time(2) 0.1 µs (1) Entering bypass mode, VIN is compared to the programmed output voltage (2.5 × VCON). When VIN − (2.5 × VCON) falls below VBP, NEG longer than TBP, NEG, the bypass FET turns on, and the switching FET turns on. (2) Bypass mode is exited when VIN − (2.5 × VCON) exceeds VBP, POS longer than TBP, POS, and PWM mode resumes. The hysteresis for the bypass detection threshold VBP, POS − VBP, NEG is always positive and will be approximately 50 mV. 6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: LM3262 |
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类似说明 - LM3262TME |
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