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ADC-101R 数据表(PDF) 4 Page - Faraday Technology

部件名 ADC-101R
功能描述  VIDEO FRONT-END MODULES
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制造商  FARADAY [Faraday Technology]
网页  http://www.faradaytech.com/
标志 FARADAY - Faraday Technology

ADC-101R 数据表(HTML) 4 Page - Faraday Technology

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Apr-01(E)
Module Details
Order Code
Gain
Black
Level
Comments
Application
MMC
Equivalent
ADC-100R
1.6
230
10-bit
FE-100H10-1
ADC-100B
1.6
230
12-bit
Composite,
Luminance (S-video),
digital
video decoder front end. High performance
applications. fs = 27 MHz
FE-100H12-1
ADC-101R
1.6
512
10-bit
FE-100H10-2
ADC-101B
1.6
512
12-bit
Chrominance , digital video decoder front end.
High performance applications. fs = 27 MHz
FE-100H12-2
ADC-110R
1.6
230
10-bit
relaxed filter
Composite,
Luminance (S-video),
digital
video decoder front end. fs = 27 MHz
FE-100M-1
ADC-111R
1.6
230
10-bit
relaxed filter
Chrominance , digital video decoder front end
fs = 27 MHz
FE-100M-2
ADC-120R
2.475
64
10-bit
CCIR-601-2 levels
Y input (Component Video) , Expanded active
video range. fs = 27 MHz
not available
ADC-121R
2.475
512
10-bit
CCIR-601-2 levels
2.75 MHz Filter
Pb,Pr input (Component video), Expanded
active video range. fs =13.5 MHz
not available
ADC-122R
2.475
64
10-bit
CCIR-601-2 levels
Double delay
Y input (Component Video) , Expanded active
video range. fs = 27 MHz
Matched digital filter delay.
Note: PROVISIONAL DATA
not available
The modules are fitted with a high performance 10-bit analogue to digital converter as standard (R-
suffix) but they are also available with a 12-bit analogue converter (B suffix)
Devices are normally supplied with a Fairchild half band filter. The units can be optionally supplied
with other compatible half band filters, or with no digital filter at the customers request.
Application Notes
The ADC modules incorporate a clamp circuit which must be fed with a back porch signal derived
on the users pcb. This can easily be generated using standard sync separators.
The user has control over digital filter inputs DEC_N, OE_N and SYNC appropriately. These inputs
allow the user to synchronise the decimation of pixel data and multiplex the outputs from modules.
For further details the user should consult the Fairchild datasheet TMC2242.
The insertion delay difference between the component modules ADC122R and ADC121R can be
eliminated by latching the Luminance data for 1 clock cycle within the application.
Note: This product is Aqueous Washable.


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